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參數(shù)資料
| 型號(hào)： | W62410 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | A Digital Speech Signal Processor(數(shù)字語(yǔ)音信號(hào)處理器) |
| 中文描述： | 8-BIT, 24.576 MHz, OTHER DSP, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 133/147頁(yè) |
| 文件大小： | 1932K |
| 代理商： | W62410 |
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NO.:
W62410 API
VERSION:
A
PAGE
133
PIO controller:
The above information is the exclusive intellectual property of Winbond Electronics and shall not be
disclosed, or reproduced without permission from Winbond.
D15
R
Vdd
Din
Dout
DMD
IO Port Configuration
PWDN
PIO 15
The I/O ports of IO 0..15 are bi-directional.
If user read the I/O port, the output latch will stay in tri-state mode and a weak pull high of about 40
μ
A will be
present to have data input.
For the transition from write to read state, a dummy read is needed.
The I/O port will stay in output tri-state condition (including the pull high) during power down mode and the
input will be gated to avoid leakage current.
Power on Reset and H/W Reset:
The TAD provides an internal power on reset while power building up for the very first time (this is a different
situation than resetting the W62410 after putting the W62410 in Power down mode). The power on reset signal
will force the Real Time Clock to be set to zero.
To ensure that the system crystal oscillate properly, the reset signal must be kept low for at least 200ms. This
reset signal will not affect the memory nor the Real Time Clock Value
Power down mode:
Operation Current Idd < 80mA at 5V
IDLE mode Idd < 40mA at 5V
Power Down Mode < 100
μ
A at 5V
A low signal on the /PWDN pin will invoke the highest priority interrupt vector to wake up the
W62410.
During power down, the system clock oscillating at 24.576Mhz, is stopped, except the Real Time
Clock and DRAM refresh. The 32768Hz oscillator will take over to support the Real Time Clock
and the DRAM refresh control signals.
The input/output pins will be kept in tri-state mode to isolate the DC path in power down mode.
After /PWDN release, a hardware reset signal must be activated again to let the W62410 wakeup and
restart.
In case of the use of Flash as external storage memory, power can be removed totally. The 32768
oscillator may be unnecessary, if
μ
Controller can maintain the Real Time Clock itself or is deemed
unnecessary for the application.
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