
NO.:
W62410 API
VERSION:
A
PAGE
123
DRAM/ Flash & Extension Port Interface:
Pin Name
(DRAM)
/RAS
O
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be disclosed, or reproduced without permission from Winbond.
I/O
Pin Name
(Flash)
EPPO0
I/O
Pin number
Description
O
1
DRAM: Row address strobe
ExtPort: Extension parallel OP 0
DRAM: Column address strobe
ExtPort: Extension serial IO [0..3]
with internal pull up
DRAM: DRAM write strobe
ExtPort: Extension port write enable
DRAM: DRAM Read strobe
ExtPort: Extension port read enable
DRAM: DRAM Address bus
ExtPort: Extension parallel OP[1..7],
Extension bit data port[4..7]
DRAM : DRAM Address bit 11
ExtPort: Extension port interrupt
DRAM: Data bus for DRAM controller
ExtPort: Extension bit data port[0..3]
Bi-directional I/O pin with
repeater
/CAS0,1,
/CAS2,3
O
EPSIO[0..3]
I/O
2,3,4,5
/MWR
O
/EPWR
O
6
/MRD
O
/EPRD
O
7
MA[0..10]
O
EPPO[1..7]
EPData[4..7]
O
I/O
8,9,11,12,13,1
,4,15,16,17,18
,19
99
MA[11]
O
IRQEx
I
MD[0..3]
I/O
EPData[0..3]
I/O
21,22,23,24
DTS ROM Interface:
Pin Name
/DTSExt
Pin number
82
I/O
I
Description
DTS ROM selection,
internal pull-up
1: Internal DTS ROM. In this mode the
following 3 pins are of no use.
0: External DTS ROM
Write Clock Pulse, active high
Read Clock Pulse, active high
Bi-directional Data Line
Wrp
Rdp
OtpData
62
61
59
O/P
O/P
I/O
TEST pins:
Pin Name
/PLLbypass
Pin number
89
I/O
I
Description
PLL bypass test mode for use in test
machine only,
internal pull up
Low : Bypass PLL, High : Normal
Output, 4xClkIn, while bit En4xF in
TEST Configuration Reg.
set to high,
otherwise tri-state
Internal pull high
, Test mode set
Leave these pins NC in normal mode
4xF
58
O
TestA
TestB
86
85
I
CHIPSET BUS Interface:
Pin Name
DATA[0..15]
Pin number
41,42,43,44,45,46,
47,48,49,51,52,53,
54,55,56,57
I/O
I/O
Description
Test pins