
Preliminary W6691
Publication Release Date: Sep 2001
92 Revision 1.1
RDOV Receive Data Overflow
A "1" indicates that the D_RFIFO is overflow. The incoming data will overwrite data in the receive FIFO. The
overflow condition will set both the status and interrupt bits. It is recommended that software must read the
RDOV bit after reading data from receive FIFO at RMR or RME interrupt. The software must abort the data
and issue a RRST command to reset the receiver if RDOV = 1.
CRCE CRC Error
Used in transparent mode only. This bit indicates the result of frame CRC check:
0 : CRC correct
1 : CRC incorrect
RMB Receive Message Aborted
Used in transparent mode only. A "1" means that a sequence of
≥
seven 1's was received and the frame is
aborted by the B1_HDLC controller. Software must issue RRST command to reset the receiver.
Note
: Bit CRCE is valid only after a RME interrupt and remains valid until the frame is acknowledged via RACK
command. RMB must be polled after a RMR/RME interrupt.
XDOW Transmit Data Overwritten
At least one byte of data has been overwritten in the B1_XFIFO. This bit is cleared only by XRST command.
XBZ Transmitter Busy
The B1_HDLC transmitter is busy when XBZ is read as "1". This bit may be polled. The XBZ bit is active when
an XMS command was issued and the message has not been completely transmitted.
8.11.8 B1_ch Address Mask Register 1
B1_ADM1
Read/Write
Address
59H
Value after reset: 00H
7
6
5
4
3
2
1
0
MA17
MA16
MA15
MA14
MA13
MA12
MA11
MA10
MA17-10 Address Mask Bits
Used in transparent mode only. These bits mask the first byte address comparisons. If the mask bit is "1", the
corresponding bit comparison with B1_ADR1 is disabled.
0: Unmask comparison
1: Mask comparison