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參數(shù)資料
型號: W6691
廠商: WINBOND ELECTRONICS CORP
英文描述: ISDN S/T Interface Transceiver
中文描述: 綜合業(yè)務數(shù)字網(wǎng)的S / T接口收發(fā)器
文件頁數(shù): 13/106頁
文件大小: 428K
代理商: W6691
Preliminary W6691
Publication Release Date: Sep 2001
13 Revision 1.1
4. PIN DESCRIPTION
TABLE 4.1 W6691 PIN DESCRIPTIONS
Note
: The suffix
"
#
"
indicates an active LOW signal. In Intel or Motorola bus mode, all unspecified pins must
be left unconnected.
Pin
Name
Pin
Number
Type
Functions
Intel Bus Mode (Enabled when MBS=HIGH)
MBS
52
I
Microprocessor bus selector (MBS). This pin must be pulled to
HIGH.
AD7-0
23, 24, 25, 26,
27, 28, 29, 30
I/O
Multiplexed address and data bus. During the address phase,
AD7-0 contains 8-bit physical address. During the data phase,
AD7-AD0 contains data.
CS#
11
I
Chip select.
ALE
10
I
Address Latch Enable. Used to latch addresses.
RD#
9
I
Read.
WR#
22
I
Write.
RST#
3
I
Reset.
INT#
64
O
Interrupt. The interrupt trigger level can be programmable by
ACTL2:INTOL. It provides two types of interrupt trigger level
including low level and high level.
Motorola Bus Mode (Enabled when MBS=LOW)
MBS
52
I
Microprocessor bus selector (MBS). This pin must be pulled to
LOW.
D7-D0
23, 24, 25, 26,
27, 28, 29, 30
I/O
Data bus.
A7-A0
12, 13, 14, 15,
16, 17, 18, 19
I
Address bus.
CS#
11
I
Chip select.
DS#
20
I
Data strobe.
RW
9
I
Read/Write identify. HIGH is for read and LOW is for write.
RST#
3
I
Reset.
INT#
64
O
Interrupt. The interrupt trigger level can be programmable by
ACTL2:INTOL. It provides two types of interrupt trigger level
including low level and high level.
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