
Preliminary W6691
Publication Release Date: Sep 2001
66 Revision 1.1
abort the data and issue a RRST command to reset the receiver if RDOV = 1. The frame overflow condition
will not set this bit.
CRCE CRC Error
This bit indicates the result of frame CRC check:
0: CRC correct
1: CRC error
RMB Receive Message Aborted
A "1" means that a sequence of seven 1's was received and the frame is aborted. Software must issue
RRST command to reset the receiver.
Note
: Normally D_RSTA register should be read by the microprocessor after a D_RME interrupt. The contents
of D_RSTA are valid only after a D_RME interrupt and remain valid until the frame is acknowledged via a
RACK bit.
8.7.11 D_ch SAPI Address Mask D_SAM
Read/Write
Address 0EH
Value after reset: 00H
7
6
5
4
3
2
1
0
SAM7
SAM6
SAM5
SAM4
SAM3
SAM2
SAM1
SAM0
This register masks(disables) the first byte address comparison of the incoming frame. If the mask bit is "1"
the corresponding bit comparisons with D_SAP1, D_SAP2 are disabled. Comparison with SAPG is always
performed.
Each HDLC frame has two address byte. The first byte is SPAI and second byte is TEI. The D_ch HDLC
controller will compare these two bytes with contents of D_SAPI1, DSAP2 and D_TEI1, D_TEI2. If the HDLC
frame SAPI matches D_SAPI1 or D_SAP2 and the HDLC frame TEI matches D_TEI1 or D_TEI2, the HDLC
frame is captured and stored in D_channel receiving FIFO. If comparison operation is enabled ( This means
that the more than one bit in D_SAM is set to “1”), except the frame with matching address is stored, others
are discarded. . If comparison operation is disabled ( This means that the all bits in D_SAM are set to “0”), all
frame with any address combination are captured and stored in receiving FIFO. The mask operation can be
programmed by each bit respectively.
The HDLC frame with SAPG and /or TEIG address are always
captured and stored.