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參數資料
| 型號： | W6691 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Transceiver |
| 中文描述： | 綜合業務數字網的S / T接口收發器 |
| 文件頁數： | 46/106頁 |
| 文件大小： | 428K |
| 代理商： | W6691 |
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Preliminary W6691
Publication Release Date: Sep 2001
46 Revision 1.1
acknowledge the interrupt. The microprocessor must handle the interrupt before more than 32 bytes of data
are received. This corresponds to a maximum microprocessor reaction time of 16 ms at 16 kbps data rate.
If the microprocessor is late in handling the interrupt, the incoming additional bytes will result in a "data
overflow" interrupt and status bit.
7.5.3 Transmission of Frames in D Channel
A 64-byte FIFO is provided in the transmit direction. If the transmit FIFO is ready (which is indicated by a
D_XFR interrupt), the micro-processor can write up to 32 bytes of data into the FIFO and use the XMS
command bit to start frame transmission. The HDLC transmitter sends the opening flag first and then sends
the data in the transmit FIFO.
The microprocessor must write the address, control and information field of a frame into the transmit FIFO.
Every time no more than 32 bytes of data are left in the transmit FIFO, the transmitter generates a D_XFR
interrupt to request another block of data. The microprocessor can then write further data to the transmit FIFO
and enables the subsequent transmission by issuing an XMS command.
If the data written to the FIFO is the last segment of a frame, the microprocessor issues the XME (Transmit
Message End) and XMS command bits to finish the frame transmission. The transmitter then transmits the
data in the FIFO and appends CRC and closing flag.
If the microprocessor fails to respond the D_XFR interrupt within a given time (16 ms), a data underrun
condition will occur. The W6691 will automatically reset the transmitter and send inter frame time fill pattern (all
1's) on D channel. The microprocessor is informed about this condition via an XDUN (Transmit Data
Underrun) interrupt in D_EXIR register. The microprocessor must wait until transmit FIFO ready (via XFR
interrupt), re-write data, and issue XMS command to re-transmit the data.
It is possible to abort a frame by issuing a D_CMDR:XRST (D channel Transmitter Reset) command. The
XRST command resets the transmitter and causes a transmit FIFO ready condition.
After the microprocessor has issued the XME command, the successful termination of transmission is
indicated by an D_XFR interrupt.
相關PDF資料 |
PDF描述 |
|---|---|
| W6691CD | ISDN S/T Interface Transceiver |
| W6691CP | ISDN S/T Interface Transceiver |
| W6692 | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| W6693A | USB Bus ISDN S/T Interface Controller(USB總線的ISDN S/T接口控制器) |
| W6694 | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W66910 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| W66910CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:TE Mode ISDN S/T-Controller with Microprocessor Interface |
| W6691CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ISDN S/T Interface Transceiver |
| W6691CP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ISDN S/T Interface Transceiver |
| W6692 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:PCI Bus ISDN S/T-Controller |
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