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參數(shù)資料
| 型號： | W6691 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Transceiver |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口收發(fā)器 |
| 文件頁數(shù)： | 45/106頁 |
| 文件大小： | 428K |
| 代理商： | W6691 |
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Preliminary W6691
Publication Release Date: Sep 2001
45 Revision 1.1
The valid address combinations are :
- SAP1 and TEI1
- SAP1 and TEI=127
- SAP2 and TEI2
- SAP2 and TEI=127
- SAPI=0 and TEI1
- SAPI=0 and TEI2
- SAPI=0 and TEI=127
The receive frame address comparisons can be disabled (masked) per bit basis by setting the D_SAM and
D_TAM registers, but comparisons with the SAPG or TEIG cannot be disabled.
7.5.2 Reception of Frames in D Channel
A 128-byte FIFO is provided in the receive direction. The data movement is handled by interrupts.
There are two interrupt sources: Receive Message Ready (D_RMR) and Receive Message End (D_RME).
The D_RMR interrupt indicates that at least 64 bytes of data have been received and the message/ frame is
not ended. Upon D_RMR interrupt, the microprocessor reads out 32 bytes of data from the FIFO. The D_RME
interrupt indicates the last segment of a message or a message with length
≤
32 bytes has been received. The
length of data is less than or equal to 32 and is specified in the D_RBCL register.
If the length of the last segment of message is 32, only D_RME interrupt is generated and the RBC4-0 bits in
D_RBCL register are 000000B.
The data between the opening flag and the CRC field are stored in D_RFIFO. For LAPD frame, this includes
the address field, control field and information field.
When a D_RMR or D_RME interrupt is generated, the micro-processor must read out the data from
D_RFIFO and issues the Receive Message Acknowledgement command (D_CMDR: RACK bit) to explicitly
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| W66910 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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| W6691CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ISDN S/T Interface Transceiver |
| W6691CP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ISDN S/T Interface Transceiver |
| W6692 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:PCI Bus ISDN S/T-Controller |
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