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參數(shù)資料
| 型號(hào)： | W6690 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Controller(ISDN S/T接口控制器) |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口控制器） |
| 文件頁(yè)數(shù)： | 50/76頁(yè) |
| 文件大小： | 471K |
| 代理商： | W6690 |
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Preliminary W6690
- 50 -
CODX3
0 Layer 1 Command Code
Value of the command code transmitted from layer 2 to layer 1.
8.1.23 S/Q Channel Receive Register SQR
Read
Address 18H
Value after reset: 0FH
7
6
5
4
3
2
1
0
MSYN
SCIE
S1
S2
S3
S4
MSYN Multiframe Synchronization
When this bit is "1", a multiframe synchronization is achived, i.e the the S/T receiver has
synchronized to the received FA and M bit patterns.
SCIE S Channel Change Interrupt Enable
This bit reflects the bit written in the SQX register.
S1-4 Received S Bits
These are the S bits received in NT to TE direction in frames 1, 6, 11 and 16. S1 is in frame 1, S2 is
in frame 6 etc.
8.1.24 S/Q Channel Transmit RegisterSQX
Write
Address 19H
Value after reset: 0FH
7
6
5
4
3
2
1
0
SCIE
Q1
Q2
Q3
Q4
SCIE S Channel Change Interrupt Enable
This bit is used to enable/disable the generation of CIR:SCC status bit and interrupt.
0: Status bit and interrupt are disabled.
1: Status bit and interrupt are enabled.
Q1-4 Transmitted Q Bits
These are the transmitted Q channels in FA bit positions in frames 1, 6, 11 and 16. Q1 is in frame 1,
Q2 is in frame 6 etc.
8.1.25 PCM Control Register
PCTL
Read/Write
Address 1AH
Value after reset: 00H
7
6
5
4
3
2
1
0
PXC
PXC PCM Cross-connect
This bit determines whether or not the PCM ports are cross-connected with the B channel ports. The
setting of PXC is independent of the BSW1
0 bits.
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| W6690ASX-1 | 制造商:Magnecraft 功能描述:Relay SSR 280V AC-IN 90A 660V AC-OUT 4-Pin |
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