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參數資料
| 型號： | W6690 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Controller(ISDN S/T接口控制器) |
| 中文描述： | 綜合業務數字網的S / T接口控制器（綜合業務數字網S / T的接口控制器） |
| 文件頁數： | 35/76頁 |
| 文件大小： | 471K |
| 代理商： | W6690 |
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Preliminary W6690
Publication Release Date: March 1998
- 35 -
Revision A1
Figure 7.8 PNP ISA Serial EEPROM Connection Diagram
The W6690 provides two types of 8-bit micro-processor interfaces:
(1) Intel multiplexed address/data bus type with control signals CSIN*, IORC*, IOWC* and ALE
(2) Motorola type with control signals CSIN*, R/W*, DS*
The selection is made via MPSEL1-0 pins as follows:
MPSEL1
MPSEL0
FUNCTION
0
0
PNP ISA mode
0
1
ISA mode
1
0
Intel multiplexed micro-processor mode
1
1
Motorola micro-processor mode
7.8.2 Cascade Structure of Interrupt Sources
The W6690 uses cascade structure to record the causes of various interrupts. The interrupt structure
is shown in Figure 7.9.
A read of the ISTA register clears all the interrupts except D_EXI, B1_EXI and B2_EXI bits. These
three bits are cleared if their corresponding extended interrupt registers are cleard.
B1_EXI bit is cleared by reading the B1_EXIR register and B2_EXI bit is cleared by reading the
B2_EXIR register. Reading of B1_EXIR or B2_EXIR register clears all the bits in it. The B1_EXIM and
B2_EXIM registers mask the corresponding bits in the B1_EXIR and B2_EXIR registers.
To clear the D_EXI bit, all the bits in D_EXIR must first be cleared. A read of the D_EXIR register
clears all the bits except the ISC bit. The ISC bit is cleared by a read of CIR and SQR registers.
Chip Select
Serial Clock
Data In
Data Out
EPCS
EPSK
EPSD
1.8 K
-2.2 K
W6690
Serial
EEPROM
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| W6690ASX-1 | 制造商:Magnecraft 功能描述:Relay SSR 280V AC-IN 90A 660V AC-OUT 4-Pin |
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| W6691 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ISDN S/T Interface Transceiver |
| W66910 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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