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參數(shù)資料
型號(hào)： W6690
廠商： WINBOND ELECTRONICS CORP
英文描述： ISDN S/T Interface Controller(ISDN S/T接口控制器)
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口控制器）
文件頁(yè)數(shù)： 14/76頁(yè)
文件大?。?/td> 471K
代理商： W6690
Preliminary W6690
- 14 -
Data transmissions on the S/T interface are arranged as frame structures. The frame is 250
μ
S long
and consists of 48 bits, which corresponds to a 192 kbit/s line rate. Each frame carries two octets of
B1 channel, two octets of B2 channel and four D channel bits. Therefore, the 2B+D data rate is 144
kbit/s. The frame structure is shown in Figure 7.1.
The frame begin is marked by a framing bit, which is followed by a DC balancing bit. The first binary
"0" following the framing bit balancing bit is of the same polarity as the framing bit balancing bit, and
subsequent binary zeros must alternate in polarity.
Figure 7.1 Frame Structure at S/T Interface
There are three wiring configurations according to I.430: point-to-point, short passive bus and
extended pass bus. They are shown in Figure 7.2.
D L F L B
1
B
1
B
1
B
1
B
1
B
1
B
1
B
1
E D A F
A
N B
2
B
2
B
2
B
2
B
2
B
2
B
2
B
2
E D MB
1
B
1
B
1
B
1
B
1
B
1
B
1
B
1
E D
S B
2
B
2
B
2
B
2
B
2
B
2
B
2
B
2
E
0
1
0
NT
→
TE
D L F L B
1
B
1
B
1
B
1
B
1
B
1
B
1
B
1
L D L F
A
L B
2
B
2
B
2
B
2
B
2
B
2
B
2
B
2
L D L B
1
B
1
B
1
B
1
B
1
B
1
B
1
B
1
L D L B
2
B
2
B
2
B
2
B
2
B
2
B
2
B
2
L D L F L
0
1
0
TE
→
NT
48 bits in 250
μ
s
2 bits offset
F = Framing bit
L = DC balancing bit
D = D channel bit
E = D channel echo bit
F
A
= Auxiliary framing bit or Q-bit
N = Bit set to a binary value N = F
A
B1 = Bit within B channel 1
B2 = Bit within B channel 2
A = Bit used for activation
S = Bit used for S channel
M = Multiframe bit
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