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參數資料
| 型號： | W6690 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Controller(ISDN S/T接口控制器) |
| 中文描述： | 綜合業務數字網的S / T接口控制器（綜合業務數字網S / T的接口控制器） |
| 文件頁數： | 45/76頁 |
| 文件大?。?/td> | 471K |
| 代理商： | W6690 |
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Preliminary W6690
Publication Release Date: March 1998
- 45 -
Revision A1
ISC Indication or S Channel Change
A change in the layer 1 indication code or multiframe S channel has been detected. The actual value
can be read from CIR or SQR registers.
TEXP D_ch Timer Expiration
Expiration occurs in the D_ch timer. The timer must be in external mode.
WEXP Watchdog Timer Expiration
Expiration occurs in the watch dog timer. A reset pulse with 125
μ
S pulse width is also generated on
the TRST pin. See D_CTL register for watch dog timer control.
8.1.9 D_ch Extended Interrupt Mask Register D_EXIM
Read/Write
Address 08H
Value after reset: FFH
7
6
5
4
3
2
1
0
RDOV
XDUN
XCOL
ISC
TEXP
WEXP
Setting the bit to "1" masks the corresponding interrupt source in D_EXIR register. Masked interrupt
status bits are read as zero. They are internally stored and pending until the mask bits are zero.
All the interrupts in D_EXIR will be masked if the IMASK:D_EXI bit is set to "1".
8.1.10 D_ch Status Register
D_STAR
Read
Address 09H
Value after reset: 00H
7
6
5
4
3
2
1
0
XDOW
XBZ
DRDY
XDOW Transmit Data Overwritten
At least one byte of data has been overwritten in the D_XFIFO. This bit is set by data overwritten
condition and is cleared only by XRES command.
XBZ Transmitter Busy
This bit indicates the D_HDLC transmitter is busy. The XBZ bit is active from the transmission of
opening flag to the transmission of closing flag.
DRDY D Channel Ready
This bit indicates the status of layer 1 D channel.
0: The layer 1 D channel is not ready. No transmission is allowed.
1: The layer 1 D channel is ready. Layer 2 can transmit data to layer 1.
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