
Preliminary W6690
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An ISC interrupt may originate from
a change in the received indication code (ICC bit in CIR register) or
a change in the received S code (SCC bit in CIR register).
The ICC interrupt can not be disabled while the SCC interrupt can be disbled by clearing the SCIE bit
in SQX register.
Bits SCC and ICC are cleared by a read of SQR and CIR.
D_EXIM register masks the corresponding bits in D_EXIR register. If the D_EXIM: ISC bit is set to
one, it masks the ICC and SCC interrupts.
The ICC or SCC bit is set whenever a new code is loaded in CIR or SQR. But if the previous register
content has not been read out in case of a code change, the new code will not be loaded. The code
registers are buffered with a FIFO size of two. Thus if several consecutive code changes are
detected, only the first and the last code is obtained at the first and second register read, respectively.
For Intel and Motorola modes, the interrupt request pin is level triggered with LOW active. It stays
active until all the bits in ISTA register are cleared. If a new status bit is set while interrupt line is
asserted, the interrupt request line makes no change. This may cause problems if W6690 is
connected to edge triggered interrupt controllers (because the new status bit does not cause edge
transition).
To solve this problem, the software can write FFH into the IMASK register and then write back the old
value. As soon as all the mask bits are set, ISTA register will temporarily be cleared to zero and the
interrupt request line goes inactive. When the old value is written in the mask register, interrupt
request line will make an edge transition if there was a queued status bit.