
Preliminary W77C32
Publication Release Date: March 1999
- 59 - Revision A1
Table 10. Serial Ports Modes
SM1
SM0
MODE
TYPE
BAUD CLOCK
FRAME
SIZE
START
BIT
STOP
BIT
9TH BIT
FUNCTION
0
0
0
Synch.
4 or 12 T
CLKs
8 bits
No
No
None
0
1
1
Asynch.
Timer 1 or 2
10 bits
1
1
None
1
0
2
Asynch.
32 or 64 T
CLKs
11 bits
1
1
0, 1
1
1
3
Asynch.
Timer 1 or 2
11 bits
1
1
0, 1
SBUF
RB8
Transmit Shift Register
Receive Shift
Register
TX SHIFT
PAROUT
D8
Internal
Data Bus
Internal
Data
Bus
TXD
RXD
Serial Port
Interrupt
SMOD=
(SMOD_1)
TCLK
RCLK
SAMPLE
Write to
SBUF
TX START
SOUT
0
1
0
1
TI
1
0
PARIN
STOP
START
LOAD
CLOCK
Read
SBUF
Timer 2 Overflow
(for Serial Port 0 only)
Timer 1
Overflow
TX CLOCK
RI
SERIAL
CONTROLLER
RX CLOCK
LOAD
SBUF
RX
START
RX SHIFT
÷
2
÷
16
1-TO-0
DETECTOR
BIT
DETECTOR
÷
16
CLOCK
SIN
D8
TB8
Figure 23: Serial Port Mode 3
Framing Error Detection
A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data
communication. Typically the frame error is due to noise and contention on the serial communication
line. The W77C32 has the facility to detect such framing errors and set a flag which can be checked
by software.
The Frame Error FE(FE_1) bit is located in SCON.7(SCON1.7). This bit is normally used as SM0 in
the standard 8051 family. However, in the W77C32 it serves a dual function and is called SM0/FE
(SM0_1/FE_1). There are actually two separate flags, one for SM0 and the other for FE. The flag that
is actually accessed as SCON.7(SCON1.7) is determined by SMOD0 (PCON.6) bit. When SMOD0 is