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參數資料
| 型號： | W77C32 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 18/71頁 |
| 文件大小： | 860K |
| 代理商： | W77C32 |
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Preliminary W77C32
- 18 -
SM2_1:Multiple processors communication. Setting this bit to 1 enables the multiprocessor
communication feature in mode 2 and 3. In mode 2 or 3, if SM2_1 is set to 1, then RI_1 will
not be activated if the received 9th data bit (RB8_1) is 0. In mode 1, if SM2_1 = 1, then RI_1
will not be activated if a valid stop bit was not received. In mode 0, the SM2_1 bit controls the
serial port 1 clock. If set to 0, then the serial port 1 runs at a divide by 12 clock of the
oscillator. This gives compatibility with the standard 8052. When set to 1, the serial clock
become divide by 4 of the oscillator clock. This results in faster synchronous serial
communication.
REN_1:Receive enable: When set to 1 serial reception is enabled, otherwise reception is
disabled.
TB8_1: This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software
as desired.
RB8_1: In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2_1 = 0, RB8_1 is the stop
bit that was received. In mode 0 it has no function.
TI_1:
Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
at the beginning of the stop bit in all other modes during serial transmission. This bit must be
cleared by software.
RI_1:
Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
halfway through the stop bits time in the other modes during serial reception. However the
restrictions of SM2_1 apply to this bit. This bit can be cleared only by software
Serial Data Buffer 1
Bit:
7
6
5
4
3
2
1
0
SBUF1.7
SBUF1.6
SBUF1.5
SBUF1.4
SBUF1.3
SBUF1.2
SBUF1.1
SBUF1.0
Mnemonic: SBUF1
Address: C1h
SBUF1.7-0: Serial data of the serial port 1 is read from or written to this location. It actually consists
of two separate 8-bit registers. One is the receive resister, and the other is the transmit
buffer. Any read access gets data from the receive data buffer, while write accesses are
to the transmit data buffer.
ROMMAP
Bit:
7
6
5
4
3
2
1
0
WS
1
-
-
-
-
-
-
Mnemonic: ROMMAP
Address: C2h
WS:
Wait State Signal Enable. Setting this bit enables the
WAIT
signal on P4.0. The device will
sample the wait state control signal
WAIT
via P4.0 during MOVX instruction. This bit is time
access protected
Power Management Register
Bit:
7
6
5
4
3
2
1
0
CD1
CD0
SWB
-
XTOFF
ALE-OFF
-
DME0
Mnemonic: PMR
Address: C4h
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W77C32_07 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-BIT MICROCONTROLLER |
| W77C32-25 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8 BIT MICROCONTROLLER |
| W77C32-40 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8 BIT MICROCONTROLLER |
| W77C32F-25 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8 BIT MICROCONTROLLER |
| W77C32F-40 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8 BIT MICROCONTROLLER |
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