
Preliminary W77C32
Publication Release Date: March 1999
- 25 - Revision A1
INSTRUCTION
The W77C32 executes all the instructions of the standard 8032 family. The operation of these
instructions, their effect on the flag bits and the status bits is exactly the same. However, timing of
these instructions is different. The reason for this is two fold. Firstly, in the W77C32, each machine
cycle consists of 4 clock periods, while in the standard 8032 it consists of 12 clock periods. Also, in
the W77C32 there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard
8032 there can be two fetches per machine cycle, which works out to 6 clocks per fetch.
The advantage the W77C32 has is that since there is only one fetch per machine cycle, the number
of machine cycles in most cases is equal to the number of operands that the instruction has. In case
of jumps and calls there will be an additional cycle that will be needed to calculate the new address.
But overall the W77C32 reduces the number of dummy fetches and wasted cycles, thereby improving
efficiency as compared to the standard 8032.
Table 2. Instructions that affect Flag settings
Instruction
Carry
Overflow
Auxiliary Carry
Instruction
Carry
Overflow
Auxiliary Carry
ADD
X
X
X
CLR C
0
ADDC
X
X
X
CPL C
X
SUBB
X
X
X
ANL C, bit
X
MUL
0
X
ANL C, bit
X
DIV
0
X
ORL C, bit
X
DA A
X
ORL C, bit
X
RRC A
X
MOV C, bit
X
RLC A
X
CJNE
X
SETB C
1
A "X" indicates that the modification is as per the result of instruction.
Table 3. Instruction Timing for W77C32
Instruction
HEX
Op-Code
Bytes
W77C32
Machine
Cycles
W77C32
Clock
Cycles
8032
Clock
Cycles
W77C32 vs.
8032 Speed
Ratio
NOP
00
1
1
4
12
3
ADD A, R0
28
1
1
4
12
3
ADD A, R1
29
1
1
4
12
3
ADD A, R2
2A
1
1
4
12
3
ADD A, R3
2B
1
1
4
12
3
ADD A, R4
2C
1
1
4
12
3
ADD A, R5
2D
1
1
4
12
3