
Preliminary W77C32
- 4 -
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The W77C32 is 8052 pin compatible and instruction set compatible. It includes the resources of the
standard 8052 such as four 8-bit I/O Ports, three 16-bit timer/counters, full duplex serial port and
interrupt sources.
The W77C32 features a faster running and better performance 8-bit CPU with a redesigned core
processor without wasted clock and memory cycles. it improves the performance not just by running
at high frequency but also by reducing the machine cycle duration from the standard 8052 period of
twelve clocks to four clock cycles for the majority of instructions. This improves performance by an
average of 1.5 to 3 times. The W77C32 also provides dual Data Pointers (DPTRs) to speed up block
data memory transfers. It can also adjust the duration of the MOVX instruction (access to off-chip
data memory) between two machine cycles and nine machine cycles. This flexibility allows the
Address
Bus
P3.0
∫
P3.7
P1.0
∫
P1.7
ALU
Port 0
Latch
Port 1
Latch
Timer
1
Timer
0
Port
0
Port
1
2 UARTs
XTAL1
PSEN
ALE
GND
V
CC
RST
XTAL2
Oscillator
Interrupt
PSW
Instruction
Decoder
&
Sequencer
Reset Block
Bus & lock
Controller
SFR RAM Address
Power control
&
Power monitor
256 bytes
RAM & SFR
Stack
Pointer
B
Addr. Reg.
Incrementor
PC
Temp Reg.
DPTR 1
T2 Register
T1 Register
ACC
Port 3
Latch
Port
3
P0.0
∫
P0.7
Port 2
Latch
Port
2
P2.0
∫
P2.7
Timer
2
1KB SRAM
DPTR
Watchdog Timer
Port 4
Latch
Port
4
P4.0
∫
P4.3