- 您現在的位置：買賣IC網 > PDF目錄363895 > W77C32 (WINBOND ELECTRONICS CORP) 8 BIT MICROCONTROLLER PDF資料下載
參數資料
| 型號： | W77C32 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 44/71頁 |
| 文件大小： | 860K |
| 代理商： | W77C32 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁
Preliminary W77C32
- 44 -
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset.
External reset
Watchdog reset
WDCON
0x0x0xx0b
0x0x01x0b
Power on reset
01000000b
The POR bit WDCON.6 is set only by the power on reset. The WTRF bit WDCON.2 is set when the
Watchdog timer causes a reset. A power on reset will also clear this bit. The EWT bit WDCON.1 is
cleared by power on resets. This disables the Watchdog timer resets. A watchdog or external reset
does not affect the EWT bit.
INTERRUPTS
The W77C32 has a two priority level interrupt structure with 12 interrupt sources. Each of the interrupt
sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts
can be globally enabled or disabled.
Interrupt Sources
The External Interrupts INT0 and
INT1
can be either edge triggered or level triggered, depending on
bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to
generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine
cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected
and the interrupts request flag IEx in TCON or EXIF is set. The flag bit requests the interrupt. Since
the external interrupts are sampled every machine cycle, they have to be held high or low for at least
one complete machine cycle. The IEx flag is automatically cleared when the service routine is called.
If the level triggered mode is selected, then the requesting source has to hold the pin low till the
interrupt is serviced. The IEx flag will not be cleared by the hardware on entering the service routine.
If the interrupt continues to be held low even after the service routine is completed, then the
processor may acknowledge another interrupt request from the same source. Note that the external
interrupts INT2 to INT5 are edge triggered only. By default, the individual interrupt flag corresponding
to external interrupt 2 to 5 must be cleared manually by software. It can be configured with hardware
cleared by setting the corresponding bit HCx in the T2MOD register. For instance, if HC2 is set
hardware will clear IE2 flag after program enters the interrupt 2 service routine.
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the
overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the
hardware when the timer interrupt is serviced. The Timer 2 interrupt is generated by a logical OR of
the TF2 and the EXF2 flags. These flags are set by overflow or capture/reload events in the timer 2
operation. The hardware does not clear these flags when a timer 2 interrupt is executed. Software has
to resolve the cause of the interrupt between TF2 and EXF2 and clear the appropriate flag.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the
time-out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the interrupt
is enabled by the enable bit EIE.4, then an interrupt will occur.
The Serial block can generate interrupts on reception or transmission. There are two interrupt sources
from the Serial block, which are obtained by the RI and TI bits in the SCON SFR and RI_1 and TI_1
in the SCON1 SFR. These bits are not automatically cleared by the hardware, and the user will have
to clear these bits using software.
All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
相關PDF資料 |
PDF描述 |
|---|---|
| W77C58 | 8 BIT MICROCONTROLLER |
| W77E058A40DL | 8-BIT MICROCONTROLLER |
| W77E058A40FL | 8-BIT MICROCONTROLLER |
| W77E058A40PL | 8-BIT MICROCONTROLLER |
| W77E058A | 8-BIT MICROCONTROLLER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W77C32_07 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-BIT MICROCONTROLLER |
| W77C32-25 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8 BIT MICROCONTROLLER |
| W77C32-40 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8 BIT MICROCONTROLLER |
| W77C32F-25 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8 BIT MICROCONTROLLER |
| W77C32F-40 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8 BIT MICROCONTROLLER |
發布緊急采購，3分鐘左右您將得到回復。