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參數資料
| 型號： | W77C32 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 21/71頁 |
| 文件大小： | 860K |
| 代理商： | W77C32 |
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Preliminary W77C32
Publication Release Date: March 1999
- 21 - Revision A1
be ignored, otherwise a negative transition detected on the T2EX pin will result in capture or
reload.
Timer 2 Run Control. This bit enables/disables the operation of timer 2. Clearing this bit will
halt the timer 2 and preserve the current count in TH2, TL2.
C/
T2
: Counter/Timer Select. This bit determines whether timer 2 will function as a timer or a
counter. Independent of this bit, the timer will run at 2 clocks per tick when used in baud rate
generator mode. If it is set to 0, then timer 2 operates as a timer at a speed depending on
T2M bit (CKCON.5), otherwise it will count negative edges on T2 pin.
CP/
RL2
:Capture/Reload Select. This bit determines whether the capture or reload function will be
used for timer 2. If either RCLK or TCLK is set, this bit will be ignored and the timer will
function in an auto-reload mode following each overflow. If the bit is 0 then auto-reload will
occur when timer 2 overflows or a falling edge is detected on T2EX pin if EXEN2 = 1.
If this bit is 1, then timer 2 captures will occur when a falling edge is detected on T2EX pin if
EXEN2 = 1.
TR2:
Timer 2 Mode Control
Bit:
7
6
5
4
3
2
-
1
0
HC5
HC4
HC3
HC2
T2CR
T2OE
DCEN
Mnemonic: T2MOD
Address: C9h
HC5:
Hardware Clear INT5 flag. Setting this bit allows the flag of external interrupt 5 to be
automatically cleared by hardware while entering the interrupt service routine.
Hardware Clear INT4 flag. Setting this bit allows the flag of external interrupt 4 to be
automatically cleared by hardware while entering the interrupt service routine.
HC4:
HC3:
Hardware Clear INT3 flag. Setting this bit allows the flag of external interrupt 3 to be
automatically cleared by hardware while entering the interrupt service routine.
Hardware Clear INT2 flag. Setting this bit allows the flag of external interrupt 3 to be
automatically cleared by hardware while entering the interrupt service routine.
T2CR: Timer 2 Capture Reset. In the Timer 2 Capture Mode this bit enables/disables hardware
automatically reset Timer 2 while the value in TL2 and TH2 have been transferred into the
capture register.
T2OE: Timer 2 Output Enable. This bit enables/disables the Timer 2 clock out function.
DCEN: Down Count Enable: This bit, in conjunction with the T2EX pin, controls the direction that
timer 2 counts in 16-bit auto-reload mode.
HC3:
Timer 2 Capture LSB
Bit:
7
6
5
4
3
2
1
0
RCAP2L.7
RCAP2L.6
RCAP2L.5
RCAP2L.4
RCAP2L.3
RCAP2L.2
RCAP2L.1
RCAP2L.0
Mnemonic: RCAP2L
Address: CAh
RCAP2L:This register is used to capture the TL2 value when a timer 2 is configured in capture mode.
RCAP2L is also used as the LSB of a 16-bit reload value when timer 2 is configured in auto-
reload mode.
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