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參數資料
| 型號： | W3100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | i2Chip W3100A |
| 中文描述： | i2Chip W3100A |
| 文件頁數： | 5/63頁 |
| 文件大小： | 557K |
| 代理商： | W3100A |
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62
/WR
I
WRITE ENABLE:
This signal is active low.
63
/RD
I
READ ENABLE:
This signal is active low.
SCL:
clock used by
I
2
C
when using
I
2
C
Interface mode
External Pull high (4.7 k
) is required.
SDA:
data used by
I
2
C
when using
I
2
C
Interface mode
External Pull high (4.7 k
) is required.
59
SCL
I
60
SDA
I/O
Table 3: W3100A Miscellaneous Signal Description
PIN#
Signal
1
RESET
I/O
I
Description
RESET:
Active High input that initializes or reinitializes the W3100A.
Asserting this pin will force a reset process to occur which will result
in all internal registers reinitializing to their default states as
specified for each bit in section x.x, and all strapping options are
reinitialized. Refer to section x.x for further detail regarding reset.
4
CLOCK
I
CLOCK:
primary clock required for internal operation of W3100A.
In general, PHY driving clock is shared for saving cost.
(25MHz is recommended)
Note) Sharing crystal source clock with multiple devices may cause
some troubles. In our reference design, we used Realtek's PHY and
one crystal for both PHY and W3100A with verification.
But for other kind of PHY, please confirm safety prior to decision.
33
EXT_CLK
I
EXTERNAL CLOCK:
supplementary clock used for MCU I/F of
W3100A.
In external clocked mode, W3100A uses this clock to interface with
MCU, and the access time of W3100A varies upon the frequency of
the external clock. Refer to xx for detailed timing diagram.
Frequency higher than 25MHz clock rate is granted.
36
/LINK
I
LINK:
This is the signal generated by Ethernet PHY to indicate the
PHY is connected to the Ethernet HUB device or other peer device.
This is active low. W3100A can knows the status of physical line
connection with this /LINK input. If /LINK is high, W3100A interprets
the physical line is disconnected. It results in TCP timeout and
connection close.
In special PHY case, LINK signal varies in time, which can be
grounded.
35
/SERIAL
I
10BASE-T SERIAL/NIBBLE SELECT:
With the selection of this
active low input, transmit and receive data are exchanged serially at
a 10 MHz clock rate on the least significant bits of the nibble-wide
MII data buses, pins TXD[0] and RXD[0], respectively. This mode is
intended for use with the W3100A connected to a PHY using a 10
Mb/s serial interface.
There is an internal pull-up resister for this pin. If this pin is left
floated externally, then the device will be configured to normal
mode. This pin must be externally pulled low (typically x k
) in
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