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參數資料
| 型號： | W3100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | i2Chip W3100A |
| 中文描述： | i2Chip W3100A |
| 文件頁數： | 17/63頁 |
| 文件大小： | 557K |
| 代理商： | W3100A |
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SHAR (Source Hardware Address Register) [R/W, 0x88 – 0x8D]
This register sets up the HA to be used in the system, which is required to be set up before executing Sys_Init
command.
SIPR (Source IP Address Register) [R/W, 0x8E – 0x91]
This register sets up the IP to be used in the system, which is required to be set up before executing Sys_Init
command.
IRTR (Initial Retry Time-value Register) [R/W, 0x92 – 0x93]
This register sets up the timer value for initial re-transmission when using the TCP, and timer value 1 is
equivalent to 100us.
Value
Timer (ms)
0x03E8
100
0x07D0
200
0x0FA0
400
RCR (Retry Count Register) [R/W, 0x94]
This register assigns the number of retry when re-transmission occurs, and timeout interrupt occurs when re-
transmission exceeds the number of retry.
RMSR (Rx data Memory Size Register) [R/W, 0x95]
This register allocates 8KB of received memory for each channel.
CH3
CH2
CH1
CH0
S1
S0
S1
S0
S1
S0
S1
S0
S1
S0
Memory size
0
0
1KB
0
1
2KB
1
0
4KB
1
1
8KB
2 bits of S1, S0 are allocated for each channel, and the memory for receiving is allocated according to the
set-up value as shown in the table above.
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