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參數(shù)資料
型號: W3100A
廠商: Electronic Theatre Controls, Inc.
英文描述: i2Chip W3100A
中文描述: i2Chip W3100A
文件頁數(shù): 38/63頁
文件大?。?/td> 557K
代理商: W3100A
MACL_RAW
MACL_RAW starting point
C0_TW_PR = A
C0_TR_PR = A
FBS >
SDS(send
data size)
MACL_RAW
sendto
cal FBS(free
buffer size)
FBS <=
C0_TW_PR -
C0_TR_PR
write data
update C0_TW_PR
send command
Send bit ==
'1'
Yes
No
No
Yes
check previous
send comand
write data from
C0_TW_PR
C0_TW_PR <=
C0_TW_PR + SDS
MACL_RAW Mode Data Reception Management
0x0000
Since reception
memory is 8KB,
mask is 0x00001FFF
0x2000
0x0200
0x0000
When C0_RW_PR is
increased by receiving data
from the peer at W3100A
0x2000
0x0200
C0_RR_PR
Rx
Data
head
0x0000
0x2000
0x0200
C0_RW_PR
0x0400
0x0400
0x0000
When C0_RW_PR is
increased by receiving data
from the peer at W3100A
0x2000
0x0200
C0_RR_PR
Rx
Data
head
0x0400
Rx
Data
head
0x0580
Rx
Data
head
0x0580
0x0000
0x2000
C0_RW_PR
0x0580
MACL_RAW Reception Memory Management
C0_RW_PR and
C0_RR_PR are
equal
(0x00000200
assumed)
C0_RW_PR is
increased to
0x00000400
(W3100A)
C0_RW_PR is
increased to
0x00000580
(W3100A)
C0_RR_PR is
increased to
0x00000400
(MCU)
C0_RR_PR is
increased to
0x00000580
(MCU)
When MCU completes
the processing of the
received data and
C0_RR_PR is increased
When MCU completes
the processing of the
received data and
C0_RR_PR is increased
MACL_RAW Mode’s Reception memory management uses 1 channel only, therefore all 8KB is allocated to
Channel 0. Above diagram illustrates the processing of 2 data after C0_WR_PR and C0_RR_PR are
equally initialized as 0x00000200.
MACL_RAW Mode Data Reception
In W3100A’s MACL_RAW Mode, the reception of the set packets are made according to the receive options
as set at C0_SOPR. As in UDP, header information is included in the received data in addition to the data,
and the header is structure as below.
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