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參數(shù)資料
| 型號： | W3100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | i2Chip W3100A |
| 中文描述： | i2Chip W3100A |
| 文件頁數(shù)： | 4/63頁 |
| 文件大小： | 557K |
| 代理商： | W3100A |
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Signal Description
Table 1: W3100A MII Signal Description
PIN#
Signal
52
51
50
49
TXD[0]
I/O
O
Description
TXD[3]
TXD[2]
TXD[1]
TRANSMIT DATA:
Nibble/Serial NRZ data output to the ENDEC
that is valid on the rising edge of TX_CLK.
In serial mode, the TXD[0] pin is used as the serial data pin, and
TXD[3:1] are ignored.
53
TXE
O
TRANSMIT ENABLE:
becomes active when the first nibble/serial
data of the packet is valid on TXD[3:0] and goes low after the last
nibble/serial data of the packet is clocked out of TXD[3:0]. This
signal connects directly to the ENDEC (PHY device). This signal
is active high.
55
TX_CLK
I
TRANSMIT CLOCK:
TX_CLK is sourced by the PHY.
TX_CLK is 2.5 MHz in 10BASE-T Nibble mode, and 25 MHz in
100BASE-T Nibble mode.
43
42
41
40
RXD[3]
RXD[2]
RXD[1]
RXD[0]
I
RECEIVE DATA:
Nibble wide receive data (synchronous to
RX_CLK) that must be driven on the falling edge of RX_CLK.
In serial mode, the RXD[0] pin is used as the data input pin which is
also clocked in on the falling edge of RX_CLK. and RXD[3:1] pins
become don’t cares.
44
RXDV/CRS
I
CARRIER SENSE:
signal provided by the ENDEC and indicates
that carrier is present. This signal is active high.
46
RX_CLK
I
RECEIVE CLOCK:
Re-synchronized clock from the ENDEC and
indicates that carrier is present.
48
COL
I
COLLISION DETECT:
becomes active when a collision has been
detected in Half Duplex modes.
This signal is asynchronous, active high and ignored during full-
duplex operation.
Table 2: W3100A MCU Interface Signal Description
PIN#
Signal
5-11
A[14-8] /
DA[6-0]
I/O
I
Description
ADDRESS PINS / DEVICE ADDRESS PINS
Used as Address[14 – 8] pin when set in MCU Bus Interface mode.
Used as Device address[6 – 0] pin for
I
2
C
Interface when set in
I
2
C
Interface mode.
14-21
A[7-0]
I
ADDRESS PINS
24-27
29-32
D[7-4]
D[3-0]
I/O
DATA PINS
61
/INT
O
INTERRUPT:
Indicates that the W3100A requires MCU attention
after reception or transmission. The interrupt is cleared by writing to
the ISR (Interrupt Status Register). All interrupts are maskable by
writing IMG (Interrupt Mask Register). This signal is active low.
64
/CS
I
CHIP SELECT:
This signal is active low.
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