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參數資料
| 型號： | W3100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | i2Chip W3100A |
| 中文描述： | i2Chip W3100A |
| 文件頁數： | 14/63頁 |
| 文件大小： | 557K |
| 代理商： | W3100A |
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C1_ISR, C2_ISR, C3_ISR (Channel 1, 2, 3 Interrupt Status Register) [R, 0x05, 0x06, 0x07]
This register notifies the outcome of the command of each Channel 1, 2 and 3.
This register becomes cleared as 0x00 by read operation.
Established notifies the completion of a connection executed by connection set-up command (Connect,
Listen).
Timeout notifies an occurrence of a time out while executing connection set-up command (Connect, Listen)
or Send command.
SInit_OK, Closed, Send_OK and Recv_OK each notifies the completion of Sock_Init, Close, Send and Recv
commands, respectively.
7
6
5
4
3
2
1
0
Recv_OK
Send_OK
Timeout
Closed
Established
SInit_OK
Bit
Symbol
Description
D0
Reserved
D1
SInit_OK
Interrupt status bit for completion of corresponding channel socket
Sock_Init command
D2
Established
Interrupt status bit for completion of corresponding channel socket
connection set-up
D3
Closed
Interrupt status bit for completion of corresponding channel socket
connection ending
D4
Timeout
Interrupt status bit for occurrence of time out during corresponding channel
socket connection set-up or data transmission
D5
Send_OK
Interrupt status bit for completion of corresponding channel socket Send
command
D6
Recv_OK
Interrupt status bit for completion of corresponding channel socket Recv
command
D7
Reserved
IR (Interrupt Register) [R/W, 0x08]
This register is used to sort channel with occurring interrupt.
C0, C1, C2 and C3 bit notify each of 0, 1, 2 and 3 channels that an interrupt has occurred. MCU can
identify which interrupt has occurred by examining the Channel Interrupt Status Register of the
corresponding channel.
C0R, C1R, C2R and C3R Bit notify that data transmission has occurred for 0, 1, 2 and 3 Channel. This
register can clear the interrupt signal by writing ‘1’ at the corresponding bit.
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