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參數資料
| 型號： | W3100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | i2Chip W3100A |
| 中文描述： | i2Chip W3100A |
| 文件頁數： | 42/63頁 |
| 文件大小： | 557K |
| 代理商： | W3100A |
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A[3:2] can be set up as ‘1’ by software after connecting the additional 4 address lines of A[3:0] and
grounding the remaining A[14:4].
Registers related to indirect bus I/F mode are listed below:
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
0x0C
IDM_OR
IND_EN
L/B
AUTO_INC
0x0D
IDM_AR0
indirect bus I/F mode address0 register
0x0E
IDM_AR1
indirect bus I/F mode address1 register
0x0F
IDM_DR
indirect bus I/F mode data register
IDM_OR (Indirect Mode Option Register) is comprised of IND_EN that determines the use of Indirect Bus
I/F mode, the L/B bit that determines byte ordering during address set-up, and the AUTO_INC bit that
automatically increases the address.
IDM_AR0 (Indirect Mode Address0 Register) designates the higher byte of the address, and IDM_AR1
(Indirect Mode Address1 Register) designates the lower byte of the address. The ordering of IDM_AR0
and IDM_AR1 varies depending upon the L/B bit set-up.
IDM_DR (Indirect Mode Data Register) displays the data to be accessed.
In order to use Indirect Bus I/F mode, IND_EN of IDM_OR needs to be setup first.
In order to read the internal register value of W3100A, the address of the internal register to be accessed
needs to be written to IDM_AR0,1. Later, when IDM_DR is read, the value of the register to be accessed is
read.
In order to write the internal register value of W3100A, the address of the internal register to be accessed
needs to be written at IDM_AR0,1. Later, the value can be written at IDM_DR.
The L/B bit of IDM_OR that sets up the order when accessing IDM_AR0,1 functions as below:
If L/B bit of IDM_OPT register = ‘0’
MSB
LSB
IDM_ADDR0(0x0D)
IDM_ADDR1(0x0E)
If L/B bit of IDM_OPT register = ‘1’
LSB
MSB
IDM_ADDR0(0x0D)
IDM_ADDR1(0x0E)
AUTO_INC Bit allows register access without setting IDM_AR0,1 for each access when continuous access
is made, where IDM_AR0,1 is automatically incremented by 1 with each IDM_DR access.
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