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參數資料
| 型號： | W3100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | i2Chip W3100A |
| 中文描述： | i2Chip W3100A |
| 文件頁數： | 15/63頁 |
| 文件大小： | 557K |
| 代理商： | W3100A |
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7
6
5
4
3
2
1
0
C3R
C2R
C1R
C0R
C3
C2
C1
C0
Bit
Symbol
Description
D0
C0
Occurrence of Channel 0 Socket Interrupt
D1
C1
Occurrence of Channel 1 Socket Interrupt
D2
C2
Occurrence of Channel 2 Socket Interrupt
D3
C3
Occurrence of Channel 3 Socket Interrupt
D4
C0R
Occurrence of Channel 0 Socket data receipt
D5
C1R
Occurrence of Channel 1 Socket data receipt
D6
C2R
Occurrence of Channel 2 Socket data receipt
D7
C3R
Occurrence of Channel 3 Socket data receipt
IMR (Interrupt Mask Register) [R/W, 0x09]
This register is used to mask an interrupt from each bit of the corresponding interrupt register. Interrupt is
enabled when the corresponding bit of the interrupt register is set by setting the corresponding bit at ‘1’.
7
6
5
4
3
2
1
0
IM_C3R
IM_C2R
IM_C1R
IM_C0R
IM_C3
IM_C2
IM_C1
IM_C0
Bit
Symbol
Description
D0
IM_C0
Channel 0 Socket Interrupt Enable.
D1
IM_C1
Channel 1 Socket Interrupt Enable.
D2
IM_C2
Channel 2 Socket Interrupt Enable.
D3
IM_C3
Channel 3 Socket Interrupt Enable.
D4
IM_C0R
Channel 0 Socket data receipt Interrupt Enable.
D5
IM_C1R
Channel 1 Socket data receipt Interrupt Enable.
D6
IM_C2R
Channel 2 Socket data receipt Interrupt Enable.
D7
IM_C3R
Channel 3 Socket data receipt Interrupt Enable.
IDM_OR (InDirect Mode Option Register) [R/W, 0x0C]
This register facilitates indirect bus I/F mode enable and option set-up.
IND_EN (indirect mode enable) bit enables indirect bus I/F mode. H/W reset is required to convert from
indirect bus I/F mode to another I/F.
L/B (Little-endian/Big-endian) bit enables the access to indirect address register as Little-endian (‘1’) or Big-
endian (‘0’).
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