
Preliminary W77LE532
- 64 -
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine
cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the
first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles,
during which the user may write to the protected bits. Once the window closes the procedure must be
repeated to access the other protected bits.
Examples of Timed Assessing are shown below.
Example 1: Valid access
MOV
MOV
MOV
TA, #0AAh
TA, #055h
WDCON, #00h 3 M/C
3 M/C
3 M/C
Note: M/C = Machine Cycles
Example 2: Valid access
MOV
MOV
NOP
SETB EWT
Example 3: Valid access
MOV
MOV
ORL
TA, #0AAh
TA, #055h
3 M/C
3 M/C
1 M/C
2 M/C
TA, #0Aah
TA, #055h
WDCON, #00000010B 3M/C
3 M/C
3 M/C
Example 4: Invalid access
MOV
MOV
NOP
NOP
CLR
TA, #0AAh
TA, #055h
POR
3 M/C
3 M/C
1 M/C
1 M/C
2 M/C
Example 5: Invalid Access
MOV
NOP
MOV
SETB EWT
TA, #0AAh
TA, #055h
3 M/C
1 M/C
3 M/C
2 M/C
In the first two examples, the writing to the protected bits is done before the 3 machine cycle window
closes. In Example 3, however, the writing to the protected bit occurs after the window has closed,
and so there is effectively no change in the status of the protected bit. In Example 4, the second write
to TA occurs 4 machine cycles after the first write, therefore the timed access window in not opened at
all, and the write to the protected bit fails.