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參數資料
| 型號： | W77LE532 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 33/85頁 |
| 文件大小： | 2458K |
| 代理商： | W77LE532 |
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Preliminary W77LE532
Publication Release Date: May 14, 2003
- 33 - Revision A1
8. INSTRUCTION
The W77LE532 executes all the instructions of the standard 8032 family. The operation of these
instructions, their effect on the flag bits and the status bits is exactly the same. However, timing of
these instructions is different. The reason for this is two fold. Firstly, in the W77LE532, each machine
cycle consists of 4 clock periods, while in the standard 8032 it consists of 12 clock periods. Also, in the
W77LE532 there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard 8032
there can be two fetches per machine cycle, which works out to 6 clocks per fetch.
The advantage the W77LE532 has is that since there is only one fetch per machine cycle, the number
of machine cycles in most cases is equal to the number of operands that the instruction has. In case
of jumps and calls there will be an additional cycle that will be needed to calculate the new address.
But overall the W77LE532 reduces the number of dummy fetches and wasted cycles, thereby
improving efficiency as compared to the standard 8032.
Table 2. Instructions that affect Flag settings
Instruction
Carry
Overflow
Auxiliary
Carry
Instruction
Carry
Overflow
Auxiliary
Carry
ADD
X
X
X
CLR C
0
ADDC
X
X
X
CPL C
X
SUBB
X
X
X
ANL C, bit
X
MUL
0
X
ANL C, bit
X
DIV
0
X
ORL C, bit
X
DA A
X
ORL C, bit
X
RRC A
X
MOV C, bit
X
RLC A
X
CJNE
X
SETB C
1
A "X" indicates that the modification is as per the result of instruction.
9. INSTRUCTION TIMING
The instruction timing for the W77LE532 is an important aspect, especially for those users who wish to
use software instructions to generate timing delays. Also, it provides the user with an insight into the
timing differences between the W77LE532 and the standard 8032. In the W77LE532 each machine
cycle is four clock periods long. Each clock period is designated a state. Thus each machine cycle is
made up of four states, C1, C2 C3 and C4, in that order. Due to the reduced time for each instruction
execution, both the clock edges are used for internal timing. Hence it is important that the duty cycle
of the clock be as close to 50% as possible to avoid timing conflicts. As mentioned earlier, the
W77LE532 does one op-code fetch per machine cycle. Therefore, in most of the instructions, the
number of machine cycles needed to execute the instruction is equal to the number of bytes in the
instruction. Of the 256 available op-codes, 128 of them are single cycle instructions. Thus more than
half of all op-codes in the W77LE532 are executed in just four clock periods. Most of the two-cycle
instructions are those that have two byte instruction codes. However there are some instructions that
have only one byte instructions, yet they are two cycle instructions. One instruction which is of
importance is the MOVX instruction. In the standard 8032, the MOVX instruction is always two
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| W77LE58F-25 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8 BIT MICROCONTROLLER |
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