
Preliminary W77LE532
Publication Release Date: May 14, 2003
- 17 - Revision A1
PORT 1
Bit:
7
6
5
4
3
2
1
0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Mnemonic: P1
Address: 90h
P1.7-0: General purpose I/O port. Most instructions will read the port pins in case of a port read
access, however in case of read-modify-write instructions, the port latch is read. Some pins
also have alternate input or output functions. This alternate functions are described below:
P1.0 : T2
P1.1 : T2EX
P1.2 : RXD1
P1.3 : TXD1
P1.4 : INT2
External I/O for Timer/Counter 2
Timer/Counter 2 Capture/Reload Trigger
Serial Port 1 Receive
Serial Port 1 Transmit
External Interrupt 2
P1.5 :
INT
P1.6 : INT4
External Interrupt 3
External Interrupt 4
3
P1.7 :
INT
External Interrupt 5
5
EXTERNAL INTERRUPT FLAG
Bit:
7
6
5
4
3
2
1
0
IE5
IE4
IE3
IE2
-
-
-
-
Mnemonic: EXIF
Address: 91h
IE5: External Interrupt 5 flag. Set by hardware when a falling edge is detected on
INT
.
IE4: External Interrupt 4 flag. Set by hardware when a rising edge is detected on INT4.
5
IE3: External Interrupt 3 flag. Set by hardware when a falling edge is detected on
INT
.
IE2: External Interrupt 2 flag. Set by hardware when a rising edge is detected on INT2.
3
PORT 4 CONTROL REGISTER A
Bit:
7
6
5
4
3
2
1
0
P41M1 P41M0
P41C1
P41C0
P40M1
P40M0 P40C1 P40C0
Mnemonic: P4CONA
Address: 92h
PORT 4 CONTROL REGISTER B
Bit:
7
6
5
4
3
2
1
0
P43M1 P43M0
P43C1
P43C0
P42M1
P42M0 P42C1 P42C0
Mnemonic: P4CONB
Address: 93h