
Preliminary W77LE532
Publication Release Date: May 14, 2003
- 23 - Revision A1
ISP ADDRESS HIGH BYTE
Bit:
7
6
5
4
3
2
1
0
A15
A14
A13
A12
A11
A10
A9
A8
Mnemonic: SFRAH
Address: ADh
High byte destination address for In System Programming operations. SFRAH and SFRAL address a
specific ROM bytes for erasure, porgramming or read.
ISP DATA BUFFER
Bit:
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Mnemonic: SFRFD
Address: AEh
In ISP mode, read/write a specific byte ROM content must go through SFRFD
register.
ISP OPERATION MODES
Bit:
7
6
5
4
3
2
1
0
BANK WFWIN
NOE
NCE
CTRL3
CTRL2 CTRL1 CTRL0
Mnemonic: SFRCN
Address: AFh
BANK: Select APFLASH banks for ISP. Set it 1 access to APFLASH1, clear it to APFLASH0.
WFWIN: Destenation ROM bank for programming, erasure and read. 0 = APFLASHx, 1 = LDFLASH.
NOE: Flash EPROM output enable.
NCE: Flash EPROM chip enable.
CTRL[3:0]: Mode Selection.
ISP Mode
BANK
WFWIN
NOE
NCE
CTRL<3:0>
SFRAH, SFRAL
SFRFD
Erase 4KB LDFLASH
0
1
1
0
0010
X
X
Erase 64K APFLASH0
0
0
1
0
0010
X
X
Erase 64K APFLASH1
1
0
1
0
0010
X
X
Program 4KB LDFLASH
0
1
1
0
0001
Address in
Data in
Program 64KB APFLASH0
0
0
1
0
0001
Address in
Data in
Program 64KB APFLASH1
1
0
1
0
0001
Address in
Data in
Read 4KB LDFLASH
0
1
0
0
0000
Address in
Data out
Read 64KB APFLASH0
0
0
0
0
0000
Address in
Data out
Read 64KB APFLASH1
1
0
0
0
0000
Address in
Data out