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參數(shù)資料
型號(hào)： W77LE532
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： 8位微控制器
英文描述： 8 BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁(yè)數(shù)： 46/85頁(yè)
文件大小： 2458K
代理商： W77LE532
Preliminary W77LE532
- 46 -
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the
overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the
hardware when the timer interrupt is serviced. The Timer 2 interrupt is generated by a logical OR of
the TF2 and the EXF2 flags. These flags are set by overflow or capture/reload events in the timer 2
operation. The hardware does not clear these flags when a timer 2 interrupt is executed. Software has
to resolve the cause of the interrupt between TF2 and EXF2 and clear the appropriate flag.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the
time-out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the interrupt is
enabled by the enable bit EIE.4, then an interrupt will occur.
The Serial block can generate interrupts on reception or transmission. There are two interrupt sources
from the Serial block, which are obtained by the RI and TI bits in the SCON SFR and RI_1 and TI_1 in
the SCON1 SFR. These bits are not automatically cleared by the hardware, and the user will have to
clear these bits using software.
All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to
disable all the interrupts, except PFI, at once.
Priority Level Structure
There are three priority levels for the interrupts, highest, high and low. The interrupt sources can be
individually set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted
by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the interrupts
themselves. This hierarchy comes into play when the interrupt controller has to resolve simultaneous
requests having the same priority level. This hierarchy is defined as shown below; the interrupts are
numbered starting from the highest priority to the lowest.
Table 7. Priority structure of interrupts
Source
Flag
Priority level
External Interrupt 0
IE0
1(highest)
Timer 0 Overflow
TF0
2
External Interrupt 1
IE1
3
Timer 1 Overflow
TF1
4
Serial Port
RI + TI
5
Timer 2 Overflow
TF2 + EXF2
6
Serial Port 1
RI_1 + TI_1
7
External Interrupt 2
IE2
8
External Interrupt 3
IE3
9
External Interrupt 4
IE4
10
External Interrupt 5
IE5
11
Watchdog Timer
WDIF
12 (lowest)
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