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參數資料
型號: W77E516F-25
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數: 58/85頁
文件大小: 596K
代理商: W77E516F-25
Preliminary W77E516
- 58 -
Mode 1
Mode 1 is similar to Mode 0 except that the counting register forms a 16 bit counter, rather than a
13 bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the
timer moves from a count of FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is
set and if enabled an interrupt will occur. The selection of the time-base in the timer mode is similar
to that in Mode 0. The gate function operates similarly to that in Mode 0.
Mode 2
In Mode 2, the timer/counter is in the Auto Reload Mode. In this mode, TLx acts as a 8 bit count
register, while THx holds the reload value. When the TLx register overflows from FFh to 00h, the
TFx bit in TCON is set and TLx is reloaded with the contents of THx, and the counting process
continues from here. The reload operation leaves the contents of the THx register unchanged.
Counting is enabled by the TRx bit and proper setting of GATE and INTx pins. As in the other
two modes 0 and 1, mode 2 allows counting of either clock cycles (clock/12 or clock/4) or pulses on
pin Tn.
1/4
1/12
T0M = CKCON.3
(T1M = CKCON.4)
C/T = TMOD.2
(C/T = TMOD.6)
0
Interrupt
T0 = P3.4
(T1 = P3.5)
TH0
(TH1)
TL0
(TL1)
TF0
(TF1)
TR0 = TCON.4
(TR1 = TCON.6)
GATE = TMOD.3
(GATE = TMOD.7)
INT0 = P3.2
(INT1 = P3.3)
7
0
TFx
7
0
Timer 1 functions are shown in brackets
1
0
1
Clock Source
Mode input
div. by 4 osc/1
div. by 64 osc/16
div. by 1024 osc/256
Figure 12: Timer/Counter Mode 2
Mode 3
Mode 3 has different operating methods for the two timer/counters. For timer/counter 1, mode 3
simply freezes the counter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8
bit count registers in this mode. The logic for this mode is shown in the figure. TL0 uses the
Timer/Counter 0 control bits C/T , GATE, TR0, INT0 and TF0. The TL0 can be used to count
clock cycles (clock/12 or clock/4) or 1-to-0 transitions on pin T0 as determined by C/T (TMOD.2).
TH0 is forced as a clock cycle counter (clock/12 or clock/4) and takes over the use of TR1 and TF1
from Timer/Counter 1. Mode 3 is used in cases where an extra 8 bit timer is needed. With Timer 0
in Mode 3, Timer 1 can still be used in Modes 0, 1 and 2., but its flexibility is somewhat limited.
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