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參數(shù)資料
型號: W77E516F-25
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 32/85頁
文件大小: 596K
代理商: W77E516F-25
Preliminary W77E516
- 32 -
OV: Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as
a result of the previous operation, or vice-versa.
F1: User Flag 1: General purpose flag that can be set or cleared by the user by software.
P:
Parity flag: Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.
Watchdog Control
Bit:
7
6
5
-
4
-
3
2
1
0
SMOD_1
POR
WDIF
WTRF
EWT
RWT
Mnemonic: WDCON
Address: D8h
SMOD_1: This bit doubles the Serial Port 1 baud rate in mode 1, 2, and 3 when set to 1.
POR: Power-on reset flag. Hardware will set this flag on a power up condition. This flag can be read
or written by software. A write by software is the only way to clear this bit once it is set.
WDIF: Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will set this bit
to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this
bit indicates that the time-out period has elapsed. This bit must be cleared by software.
WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a
reset. Software can read it but must clear it manually. A power-fail reset will also clear the
bit. This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog
timer will have no affect on this bit.
EWT: Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function.
RWT: Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also
helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before
time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog
timer reset will be generated if EWT is set. This bit is self-clearing by hardware.
The WDCON SFR is set to a 0x0x0xx0b on an external reset. WTRF is set to a 1 on a Watchdog
timer reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set
to 1 by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets.
All the bits in this SFR have unrestricted read access. POR, EWT, WDIF and RWT require Timed
Access procedure to write. The remaining bits have unrestricted write accesses. Please refer TA
register discription.
TA
WDCON REG
CKCON
MOV TA, #AAH
MOV TA, #55H
SETB WDCON.0 ; Reset watchdog timer
ORL CKCON, #11000000B ; Select 26 bits watchdog timer
MOV TA, #AAH
MOV TA, #55H
ORL WDCON, #00000010B ; Enable watchdog
REG
C7H
D8H
8EH
REG
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