
Preliminary W77E516
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WS: Wait State Signal Enable. Setting this bit enables the WAIT signal on P4.0. The device will
sample the wait state control signal WAIT via P4.0 during MOVX instruction. This bit is
time access protected.
TA
REG
C7H
C2H
8EH
WSCON
CKCON REG
MOV
TA, #AAH
MOV
TA, #55H
ORL
WSCON, #10000000B; Set WS bit and stretch value = 0 to enable wait signal.
REG
Power Management Register
Bit:
7
6
5
4
3
2
1
0
CD1
CD0
SWB
-
-
ALE-OFF
-
DME0
Mnemonic: PMR
Address: C4h
CD1, CD0: Clock Divide Control. These bit selects the number of clocks required to generate one
machine cycle. There are three modes including divide by 4, 64 or 1024. Switching
between modes must first go back divide by 4 mode. For instance, to go from 64 to
1024 clocks/machine cycle the device must first go from 64 to 4 clocks/machine cycle,
and then from 4 to 1024 clocks/machine cycle.
CD1,
0
0
1
1
CD0
0
1
0
1
Clocks/machine Cycle
Reserved
4
64
1024
SWB: Switchback Enable. Setting this bit allows an enabled external interrupt or serial port activity
to force the CD1, CD0 to divide by 4 state (0,1). The device will switch modes at the start of
the jump to interrupt service routine while a external interrupt is enabled and actually
recognized by micro controller. While a serial port reception, the switchback occurs at the
start of the instruction following the falling edge of the start bit.
ALE0FF: This bit disables the expression of the ALE signal on the device pin during all on-board
program and data memory accesses. External memory accesses will automatically
enable ALE independent of ALEOFF.
0 = ALE expression is enable; 1 = ALE expression is disable
DME0: This bit determines the on-chip MOVX SRAM to be enabled or disabled. Set this bit to 1 will
enable the on-chip 1KB MOVX SRAM.