
Preliminary W77E516
- 52 -
Reset State
Most of the SFRs and registers on the device will go to the same condition in the reset state. The
Program Counter is forced to 0000h and is held there as long as the reset condition is applied.
However, the reset state does not affect the on-chip RAM. The data in the RAM will be preserved
during the reset. However, the stack pointer is reset to 07h, and therefore the stack contents will be
lost. The RAM contents will be lost if the V
DD
falls below approximately 2V, as this is the minimum
voltage level required for the RAM to operate normally. Therefore after a first time power on reset the
RAM contents will be indeterminate. During a power fail condition, if the power falls below 2V, the RAM
contents are lost. Hence it should be assumed that after a power on/fail reset, POR = 1, the RAM
contents are lost.
After a reset most SFRs are cleared. Interrupts and Timers are disabled. The Watchdog timer is
disabled if the reset source was a POR. The port SFRs have FFh written into them which puts the port
pins in a high state. Port 0 floats as it does not have on-chip pull-ups.
Table 6. SFR Reset Value
SFR NAME
RESET VALUE
SFR NAME
RESET VALUE
P0
11111111b
IE
00000000b
SP
00000111b
SADDR
00000000b
DPL
00000000b
P3
11111111b
DPH
00000000b
IP
x0000000b
DPL1
00000000b
SADEN
00000000b
DPH1
00000000b
T2CON
00000000b
DPS
00000000b
T2MOD
00000x00b
PCON
00xx0000b
RCAP2L
00000000b
TCON
00000000b
RCAP2H
00000000b
TMOD
00000000b
TL2
00000000b
TL0
00000000b
TH2
00000000b
TL1
00000000b
TA
11111111b
TH0
00000000b
PSW
00000000b
TH1
00000000b
WDCON
0x0x0xx0b
CKCON
00000001b
ACC
00000000b
xxx
00000b
P1
11111111b
EIE
SCON
00000000b
xxxxxxxx
b
B
00000000b
SBUF
EIP
xxx00000b
P2
11111111b
PC
00000000b
SADDR1
00000000b
SADEN1
00000000b
xxxxxxxx
b
SCON1
00000000b
SBUF1
ROMMAP
01
xxxxxx
b
PMR
010xx0x0b
EXIF
0000
xxx
0b
xxxx
1111b
STATUS
000x0000b
P4