
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-62 -
Contains the Monitor channel data transmitted in GCI Monitor channel 0 according to the Monitor channel protocol.
8.1.30 Monitor Channel 0 Interrupt Register
Value after reset: 00H
7
6
5
MO0I Read_clear
Address 74H/1DH
4
3
2
1
0
MDR
0
MER
0
MDA
0
MAB
0
MDR0
Monitor channel 0 Data Receive
MER0
Monitor channel 0 End of Reception
MDA0
Monitor channel 0 Data Acknowledged
The remote end has acknowledged the Monitor byte being transmitted.
MAB0
Monitor channel 0 Data Abort
8.1.31 Monitor Channel 0 Control Register
Value after reset: 00H
7
6
5
0
0
0
MRIE0 Monitor Channel 0 Receive Interrupt Enable
Monitor channel interrupt status MDR0, MER0 generation is enabled (1) or masked (0).
MRC0 MR Bit Control
Determines the value of the MR bit:
0: MR bit always 1. In addition, the MDR0 interrupt is blocked, except for the first byte of a packet (if MRE=1).
1: MR internally controlled by the W6692A according to Monitor channel protocol. In addition, the MDR0 interrupt
is enabled for all received bytes according to the Monitor channel protocol (if MRE=1).
MXIE0 Monitor channel 0 Transmit Interrupt Enable
Monitor interrupt status MDA0, MAB0 generation is enabled (1) or masked (0).
MXC0 MX bit Control
Determines the value of the MX bit:
0: MX always 1.
1: MX internally controlled by the W6692A according to Monitor channel protocol.
MO0C
Read/Write Address 78H/1EH
4
0
3
2
1
0
MRIE0
MRC0
MXIE0
MXC0
8.1.32 GCI Mode Control/Status Register
7CH/1FH
GCR Read/Write
Address