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參數(shù)資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務(wù)數(shù)字網(wǎng)的PCI總線的S / T的接口控制器） |
| 文件頁數(shù)： | 24/98頁 |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-24 -
A 96 kHz continuous pulse with alternating polarities is sent.
Send Single Pulses
A 2 KHz , isolated pulse with alternating polarities is sent.
Layer 1 Reset
A layer 1 reset command forces the transmission of INFO 0 and disables the S line awake detector. Thus activation from NT
is not possible. There is no indication in reset state. The reset state can be left only with ECK command.
TABLE 7.2 LAYER 1 COMMAND CODES
Command
Enable clock
Layer 1 reset
Send continuous pulses
Send single pulses
Activate request at priority 8
Activate request at priority 10
Enable analog loopback
Deactivate layer 1
Symbol
ECK
RST
SCP
SSP
AR8
AR10
EAL
DRC
Code
0000
0001
0100
0010
1000
1001
1010
1111
Description
Enable internal clocks
Layer 1 reset
Send continuous pulses at 96 kHz
Send isolated pulses at 2 kHz
Activate layer 1 and set D channel priority level to 8
Activate layer 1 and set D channel priority to 10
Enable analog loopback
Deactivate layer 1 and disable internal clocks
TABLE 7.3 LAYER 1 INDICATION CODES
Indication
Clock Enabled
Deactivate request downstream DRD
Level detected
Activate request downstream
Test indication
Symbol
CE
Code
0111
0000
0100
1000
1010
Descriptions
Internal clocks are enabled
Deactivation request by S interface, i.e INFO 0 received
Signal received, receiver not synchronous
INFO 2 received
Analog loopback activated or continuous zeros or single zeros
transmitted
Level detected during test function
INFO 4 received, D channel priority is 8 or 9
LD
ARD
TI
Awake test indication
Activate indication with priority
class 1
Activate indication with priority
class 2
Clock disabled
ATI
AI8
1011
1100
AI10
1101
INFO 4 received, D channel priority is 10 or 11
CD
1111
Layer 1 deactivated, internal clocks are disabled
7.2.3.2 State Transition Diagrams
The followings are the state transition diagrams, which implement the activation/deactivation state matrix in I.430 (TABLE
5/I.430). The "command" and "s receive" entries in each state octagon keep the state, the "indication" and "s transmit" entries in
each state octagon are the state outputs. For example, at "F3 Deactivated with clock" state, the layer 1 will stay at this state if the
command is "ECK" and the INFO 0 is received on S interface. At this state, it provides "CE" indication to the microprocessor
and transmits INFO 0 on S interface. The "AR8/10" command causes transition to F4 and non-INFO 0 signal causes transition to
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