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參數資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器） |
| 文件頁數： | 37/98頁 |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-37 -
message with length
≤
64 bytes has been received. The length of data is less than or equal to 64 and is specified in the D_RBCL
register.
If the length of the last segment of message is 64, only D_RME interrupt is generated and the RBC5-0 bits in D_RBCL
register are 000000B.
The data between the opening flag and the CRC field are stored in D_RFIFO. For LAPD frame, this includes the address
field, control field and information field.
When a D_RMR or D_RME interrupt is generated, the micro-processor must read out the data from D_RFIFO and issues the
Receive Message Acknowledgement command (D_CMDR: RACK bit) to explicitly acknowledge the interrupt. The
microprocessor must handle the interrupt before more than 64 bytes of data are received. This corresponds to a maximum
microprocessor reaction time of 32 ms at 16 kbps data rate.
If the microprocessor is late in handling the interrupt, the incoming additional bytes will result in a "data overflow" interrupt
and status bit.
7.6.3 Transmission of Frames in D Channel
A 128-byte FIFO is provided in the transmit direction. If the transmit FIFO is ready (which is indicated by a D_XFR
interrupt), the micro-processor can write up to 64 bytes of data into the FIFO and use the XMS command bit to start frame
transmission. The HDLC transmitter sends the opening flag first and then sends the data in the transmit FIFO.
The microprocessor must write the address, control and information field of a frame into the transmit FIFO.
Every time no more than 64 bytes of data are left in the transmit FIFO, the transmitter generates a D_XFR interrupt to request
another block of data. The microprocessor can then write further data to the transmit FIFO and enables the subsequent
transmission by issuing an XMS command.
If the data written to the FIFO is the last segment of a frame, the microprocessor issues the XME (Transmit Message End)
and XMS command bits to finish the frame transmission. The transmitter then transmits the data in the FIFO and appends CRC
and closing flag.
If the microprocessor fails to respond the D_XFR interrupt within a given time (32 ms), a data underrun condition will occur.
The W6692A will automatically reset the transmitter and send inter frame time fill pattern (all 1's) on D channel. The
microprocessor is informed about this condition via an XDUN (Transmit Data Underrun) interrupt in D_EXIR register. The
microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit
the data.
It is possible to abort a frame by issuing a D_CMDR:XRST (D channel Transmitter Reset) command. The XRST command
resets the transmitter and causes a transmit FIFO ready condition.
After the microprocessor has issued the XME command, the successful termination of transmission is indicated by an D_XFR
interrupt.
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