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參數資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器） |
| 文件頁數： | 3/98頁 |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-3 -
TABLE OF CONTENTS
1. GENERAL DESCRIPTION
................................................................................................................................................. 8
2. FEATURES
............................................................................................................................................................................ 8
3. PIN CONFIGURATION
..................................................................................................................................................... 9
4. PIN DESCRIPTION
........................................................................................................................................................... 12
5
. SYSTEM DIAGRAM AND APPLICATIONS
................................................................................................................ 15
6. BLOCK DIAGRAM
........................................................................................................................................................... 16
7. FUNCTIONAL DESCRIPTIONS
..................................................................................................................................... 17
7.1 M
AIN
B
LOCK
F
UNCTIONS
................................................................................................................................................... 17
7.2 L
AYER
1 F
UNCTIONS
D
ESCRIPTIONS
................................................................................................................................... 18
7.2.1 S/T Interface Transmitter/Receiver ............................................................................................................................ 18
7.2.2 Receiver Clock Recovery And Timing Generation...................................................................................................... 22
7.2.3 Layer 1 Activation/Deactivation................................................................................................................................ 22
7.2.3.1 States Descriptions And Command/Indication Codes.......................................................................................... 22
7.2.3.2 State Transition Diagrams................................................................................................................................... 24
7.2.4 D Channel Access Control......................................................................................................................................... 28
7.2.5 Frame Alignment....................................................................................................................................................... 28
7.2.5.1 FAinfA_1fr......................................................................................................................................................... 29
7.2.5.2 FAinfB_1fr ......................................................................................................................................................... 29
7.2.5.3 FAinfD_1fr......................................................................................................................................................... 29
7.2.5.4 FAinfA_kfr......................................................................................................................................................... 29
7.2.5.5 FAinfB_kfr ......................................................................................................................................................... 29
7.2.5.6 FAinfD_kfr......................................................................................................................................................... 30
7.2.5.7 Faregain.............................................................................................................................................................. 30
7.2.6 Multiframe Synchronization....................................................................................................................................... 30
7.2.7 Test Functions ........................................................................................................................................................... 31
7.3 S
ERIAL
I
NTERFACE
B
US
..................................................................................................................................................... 33
7.4 B C
HANNEL
S
WITCHING
.................................................................................................................................................... 33
7.6 D C
HANNEL
HDLC C
ONTROLLER
...................................................................................................................................... 35
7.6.1 D Channel Message Transfer Modes.......................................................................................................................... 36
7.6.2 Reception of Frames in D Channel ............................................................................................................................ 36
7.6.3 Transmission of Frames in D Channel....................................................................................................................... 37
7.7 B C
HANNEL
HDLC C
ONTROLLER
...................................................................................................................................... 38
7.7.1 Reception of Frames in B Channel
...................................................................................................................... 38
7.7.2 Transmission of Frames in B Channel........................................................................................................................ 39
7.8 GCI M
ODE
S
ERIAL
I
NTERFACE
B
US
.................................................................................................................................... 40
7.8.1 GCI Mode C/I0 Channel Handling ............................................................................................................................ 41
7.8.2 GCI Mode Monitor Channel Handling....................................................................................................................... 41
7.9 PCI/MP I
NTERFACE
C
IRCUIT
............................................................................................................................................. 42
7.9.1 PCI Slave Mode And Configuration Serial EEPROM ................................................................................................ 42
7.9.2 8-bit Microprocessor Interface .................................................................................................................................. 44
7.10 P
ERIPHERAL
C
ONTROL
..................................................................................................................................................... 44
8. REGISTER DESCRIPTIONS ............................................................................................................................................. 46
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