
Data Sheet
W6692A PCI ISDN S/T-Controller
Read/Write Address 30H/0CH
Publication Release Date:
Mar,2000
Revision 1.0
-55 -
8.1.13 D_ch SAPI1 Register D_SAP1
Value after reset: 00H
7
6
SA17
SA16
SA15
This register contains the first choice of the first byte address of received frame. For LAPD frame, SA17 - SA12 is the SAPI
value, SA11 is C/R bit and SA10 is zero.
5
4
3
2
1
0
SA14
SA13
SA12
SA11
SA10
8.1.14 D_ch SAPI2 Register D_SAP2
Value after reset: 00H
7
6
SA27
SA26
SA25
This register contains the second choice of the first byte address of received frame. For LAPD frame, SA27 - SA22 is the
SAPI value, SA21 is C/R bit and SA20 is zero.
Read/Write Address 34H/0DH
5
4
3
2
1
0
SA24
SA23
SA22
SA21
SA20
8.1.15 D_ch TEI Address Mask D_TAM
Value after reset: 00H
7
6
5
TAM7
TAM6
TAM5
This register masks (disables) the second byte address comparison of the incoming frame. If the mask bit is "1" the
corresponding bit comparisons with D_TEI1, D_TEI2 are disabled. Comparison with TEIG is always performed.
Note
: For the LAPD frame, the least significant bit is the EA =1 bit.
Read/Write Address 38H/0EH
4
3
2
1
0
TAM4
TAM3
TAM2
TAM1
TAM0
8.1.16 D_ch TEI1 Register D_TEI1
Value after reset: 00H
7
6
TA17
TA16
TA15
TA17 - TA10
This register contains the first choice of the second byte address of received frame. For LAPD frame, TA17 - TA11 is the TEI
value, TA10 is EA = 1.
Read/Write
Address 3CH/0FH
5
4
3
2
1
0
TA14
TA13
TA12
TA11
TA10