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參數資料
| 型號： | W3H64M72E-533ESI |
| 英文描述： | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| 中文描述： | 64米× 72 DDR2 SDRAM的208 PBGA封裝多芯片封裝 |
| 文件頁數： | 9/30頁 |
| 文件大小： | 956K |
| 代理商： | W3H64M72E-533ESI |
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W3H64M72E-XSBX
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
MODE REGISTER (MR)
The mode register is used to define the specific mode of
operation of the DDR2 SDRAM. This definition includes
the selection of a burst length, burst type, CL, operating
mode, DLL RESET, write recovery, and power-down mode,
as shown in Figure 5. Contents of the mode register can be
altered by re-executing the LOAD MODE (LM) command.
If the user chooses to modify only a subset of the MR
variables, all variables (M0–M14) must be programmed
when the command is issued.
The mode register is programmed via the LM command
(bits BA2–BA0 = 0, 0, 0) and other bits (M12–M0) will
retain the stored information until it is programmed again
or the device loses power (except for bit M8, which is
self-clearing). Reprogramming the mode register will
not alter the contents of the memory array, provided it is
performed correctly.
The LM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts
are in progress. The controller must wait the specified
time
t
MRD before initiating any subsequent operations
such as an ACTIVE command. Violating either of these
requirements will result in unspecified operation.
BURST LENGTH
Burst length is defined by bits M0–M3, as shown in Figure
5. Read and write accesses to the DDR2 SDRAM are
burst-oriented, with the burst length being programmable
to either four or eight. The burst length dete rmines
the maximum number of column locations that can be
accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where
Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within the
block. The programmed burst length applies to both READ
and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved. The burst type is selected
via bit M3, as shown in Figure 5. The ordering of accesses
within a burst is determined by the burst length, the burst
type, and the starting column address, as shown in Table
2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst
mode only. For 8-bit burst mode, full interleave address
ordering is supported; however, sequential address
ordering is nibble-based.
Burst Length
CAS# Latency BT
PD
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
A10
A12 A11
BA0
BA1
10
11
12
13
0
1
14
Burst Length
Reserved
Reserved
4
8
Reserved
Reserved
Reserved
Reserved
M0
0
1
0
1
0
1
0
1
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
0
1
Burst Type
Sequential
Interleaved
M3
CAS Latency (CL)
Reserved
Reserved
Reserved
3
4
5
6
Reserved
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
0
1
Mode
Normal
Test
M7
15
MR
DLL TM
0
1
DLL Reset
No
Yes
M8
WRITE RECOVERY
Reserved
2
3
4
5
6
Reserved
Reserved
M9
0
1
0
1
0
1
0
1
M10
0
0
1
1
0
0
1
1
M11
0
0
0
0
1
1
1
1
WR
A13
0
1
0
1
Mode Register Definition
Mode Register (MR)
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
M15
0
0
1
1
0
1
PD mode
Fast Exit
(Normal)
Sow Exit
(Low Power)
M12
M14
FIGURE 5 – MODE REGISTER (MR) DEFINITION
Note: 1. Not used on this part
相關PDF資料 |
PDF描述 |
|---|---|
| W3H64M72E-533ESM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SB | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBC | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBI | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W3H64M72E-533ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SB | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBC | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H64M72E-533SBI | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H64M72E-533SBM | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA MIL-TEMP. - Bulk |
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