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參數資料
| 型號： | W3H64M72E-533ESI |
| 英文描述： | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| 中文描述： | 64米× 72 DDR2 SDRAM的208 PBGA封裝多芯片封裝 |
| 文件頁數： | 14/30頁 |
| 文件大小： | 956K |
| 代理商： | W3H64M72E-533ESI |
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W3H64M72E-XSBX
14
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make
the command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. Bits E3–E5 define the value
of AL, as shown in Figure 7. Bits E3–E5 allow the user
to program the DDR2 SDRAM with an inverse AL of 0, 1,
2, 3, or 4 clocks. Reserved states should not be used as
unknown operation or incompatibility with future versions
may result.
In this operation, the DDR2 SDRAM allows a READ or
WRITE command to be issued prior to
t
RCD (MIN) with
the requirement that AL ≤
t
RCD (MIN). A typical application
using this feature would set AL =
t
RCD (MIN) - 1x
t
CK. The
READ or WRITE command is held for the time of the AL
before it is issued internally to the DDR2 SDRAM device.
RL is controlled by the sum of AL and CL; RL = AL+CL.
Write latency (WL) is equal to RL minus one clock; WL =
AL + CL - 1 x
t
CK.
A9
A7 A 6 A5 A4 A3
A8
A2
A1 A0
Exten ded Mo de
Register (Ex)
Address Bus
9
7
6
5
4
3
8
2
1
0
A10
A12
A11
BA0
BA1
10
0
1
11
0
1
12
0
1
13
0
1
14
15
A13
0
1
0
1
Mode Register Definition
M15
0
0
1
1
M14
EMR2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
High Temperature Self Refresh rate enable
Industrial temperature option;
use if T
C
exceeds 85° C
E7
0
1
BA2
16
M16
0
0
0
0
Mode register (MR)
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
Commercial temperature default
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
相關PDF資料 |
PDF描述 |
|---|---|
| W3H64M72E-533ESM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SB | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBC | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBI | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W3H64M72E-533ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SB | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBC | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H64M72E-533SBI | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H64M72E-533SBM | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA MIL-TEMP. - Bulk |
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