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參數資料
| 型號： | W3H64M72E-533ESI |
| 英文描述： | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| 中文描述： | 64米× 72 DDR2 SDRAM的208 PBGA封裝多芯片封裝 |
| 文件頁數： | 5/30頁 |
| 文件大小： | 956K |
| 代理商： | W3H64M72E-533ESI |
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W3H64M72E-XSBX
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
TABLE – 1 BALL DESCRIPTIONS
(continued)
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA2–BA0) or all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD
MODE command.
Data input/output: Bidirectional data bus
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
Power Supply: 1.8V ±0.1V
DQ Power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity
SSTL_18 reference voltage.
Ground
No connect: These balls should be left unconnected.
Future use; address bits A14 and A15 are reserved for future densities.
A0-A12
Input
DQ0-71
I/O
UDQS, UDQS#
I/O
LDQS, LDQS#
I/O
V
CC
V
CCQ
V
REF
V
SS
NC
DNU
Supply
Supply
Supply
Supply
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相關PDF資料 |
PDF描述 |
|---|---|
| W3H64M72E-533ESM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SB | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBC | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBI | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W3H64M72E-533ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SB | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBC | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H64M72E-533SBI | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H64M72E-533SBM | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA MIL-TEMP. - Bulk |
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