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參數資料
| 型號： | W3H64M72E-533ESI |
| 英文描述： | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| 中文描述： | 64米× 72 DDR2 SDRAM的208 PBGA封裝多芯片封裝 |
| 文件頁數： | 8/30頁 |
| 文件大小： | 956K |
| 代理商： | W3H64M72E-533ESI |
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W3H64M72E-XSBX
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
NOTES:
1.
Applying power; if CKE is maintained below 0.2 x V
CCQ
, outputs remain disabled.
To guarantee R
TT
(ODT resistance) is off, VREF must be valid and a low level must
be applied to the ODT ball (all other inputs may be undefined, I/Os and outputs
must be less than V
CCQ
during voltage ramp time to avoid DDR2 SDRAM device
latch-up). At least one of the following two sets of conditions (A or B) must be
met to obtain a stable supply state (stable supply defined as V
CC
, V
CCQ
,V
REF
, and
V
TT
are between their minimum and maximum values as stated in DC Operating
Conditions table):
A. single power source) The V
CC
voltage ramp from 300mV to V
CC
(MIN) must
take no longer than 200ms; during the V
CC
voltage ramp, |V
CC
- V
CCQ
| ≤ 0.3V.
Once supply voltage ramping is complete (when V
CCQ
crosses V
CC
(MIN), DC
Operating Conditions table specifications apply.
V
CC
, V
CCQ
are driven from a single power converter output
V
TT
is limited to 0.95V MAX
V
REF
tracks V
CCQ/2
; V
REF
must be within ±0.3V with respect to V
CCQ/2
during
supply ramp time.
V
CCQ
≥ V
REF
at all times
B. multiple power sources) V
CC
≥ V
CCQ
must be maintained during supply voltage
ramping, for both AC and DC levels, until supply voltage ramping completes
(V
CCQ
crosses V
CC
[MIN]). Once supply voltage ramping is complete, DC
Operating Conditions table specifications apply.
Apply V
CC
before or at the same time as V
CCQ
; V
CC
voltage ramp time must
be ≤ 200ms from when V
CC
ramps from 300mV to V
CC
(MIN)
Apply V
CCQ
before or at the same time as V
TT
; the V
CCQ
voltage ramp time
from when V
CC
(MIN) is achieved to when V
CCQ
(MIN) is achieved must be ≤
500ms; while V
CC
is ramping, current can be supplied from V
CC
through the
device to V
CCQ
V
REF
must track V
CCQ/2
, V
REF
must be within ±0.3V with respect to V
CCQ/2
during supply ramp time; V
CCQ
≥ V
REF
must be met at all times
Apply V
TT
; The V
TT
voltage ramp time from when V
CCQ
(MIN) is achieved to
when
VTT
(MIN) is achieved must be no greater than 500ms
CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during
device power-up prior to V
REF
. being stable. After state T0, Cke is required to have
SSTL_18 input levels. Once CKE transitions to a high level, it must stay HIGH for
the duration on the initialization sequence.
PRE = PRECHARGE command, LM = LOAD MODE command, MR = Mode
Register, EMR = extended mode register, EMR2 = extended mode register 2,
EMR3 = extended mode register 3, REF = REFRESH command, ACT = ACTIVE
command, A10 = PRECHARGE ALL, CODE = desired value for mode registers
(blank addresses are required to be decoded), VALID - any valid command/
address, RA = row address, bank address.
DM represents UDM & LDM, DQS represents, UDQS, UDQS#, LDQS, LDQS#,
RDQS, RDQS#, DQ represents DQ0-71.
For a minimum of 200μs after stable power and clock (CK, CK#), apply NOP or
DESELECT commands, then take CKE HIGH.
Wait a minimum of 400ns, then issue a PRECHARGE ALL command.
Issue a LOAD MODE command to the EMR(2). (To issue an EMR(3) command,
provide LOW to BA2 and BA0, and provide HIGH to BA1.) Set register E7 to "0" or
"1;" all others must be "0".
Issue LOAD MODE command to the EMR(3). (to issue and EMR(3) command,
provide HIGH to BA0 = 1, BA1 = 1, and BA2 = 0.) Set all registers to "0".
Issue a LOAD MODE command to the EMR to enable DLL. To issue a CLL
2.
3.
4.
5.
6.
7.
8.
9.
ENABLE command provide LOW to BA1, BA2 and A0; provide HIGH to BA0. Bits
E7, E8 and E9 can be set to "0" or "1;" Micron recommends setting them to "0".
10. Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is
required to lock the DLL. (To issue a DLL RESET, provide HIGH to A8 and provide
LOW to BA2 = BA1 = BA0 = 0.) CKE must be HIGH the entire time. .
11. Issue PRECHARGE ALL command.
12. Issue two or more REFRESH commands.
13. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e.,
to program operating parameters without resetting the DLL). To access the mode
registers, BA0 = 0, BA1 = 0, BA2 = 0.
14. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits
E7, E8, and E9 to “1,” and then setting all other desired parameters. To access the
extended mode register, BA2 = 0, BA1 = 0, BA0 = 1.
15. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7,
E8, and E9 to “0,” and then setting all other desired parameters. To access the
extended mode registers, BA2 = 0, BA1 = 0, BA0 = 1.
16. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock
cycles after the DLL RESET at Tf0.
相關PDF資料 |
PDF描述 |
|---|---|
| W3H64M72E-533ESM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SB | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBC | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBI | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W3H64M72E-533ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SB | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBC | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H64M72E-533SBI | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H64M72E-533SBM | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA MIL-TEMP. - Bulk |
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