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參數資料
| 型號： | W29S201 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 128K×16bit CMOS Flash Memory With Synchronous Burst Read(具有同步脈沖讀模式的128K×16位CMOS閃速存儲器) |
| 中文描述： | 128K的× 16位的CMOS同步突發讀取快閃記憶體（具有同步脈沖讀模式的128K的× 16位的CMOS閃速存儲器） |
| 文件頁數： | 5/31頁 |
| 文件大小： | 253K |
| 代理商： | W29S201 |
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Preliminary W29S201
Publication Release Date: April 1999
- 5 -
Revision A1
Sector Erase Operation
The three sectors, main memory and two parameters blocks, can be erased individually by initiating a
six-word command sequence. Sector address is latched on the falling WE edge of the sixth cycle while
the 30(hex) data input command is latched at the rising edge of WE. After the command loading cycle,
the device enters the internal sector erase mode, which is automatically timed and will be completed in a
fast 100 mS (typical). The host system is not required to provide any control or timing during this
operation. The device will automatically return to normal read mode after the erase operation completed.
Data polling and/or Toggle Bits can be used to detect end of erase cycle.
When the boot block lockout feature is inactivated, the boot block and the main memory block will be
erased together. Once the boot block is locked, only the main memory block will be erased by the
execution of sector erase operation.
Program Operation
The W29S201 is programmed on a word-by-word basis. Program operation can only change logical data
"1" to logical data "0" The erase operation (changed entire data in main memory and/or boot block from
"0" to "1" is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will internally enter the program operation immediately after the word-program
command is entered. The internal program timer will automatically time-out (50
μ
S max. - T
BP
) once
completed and return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of
program cycle.
Hardware Data Protection
The integrity of the data stored in the W29S201 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The programming operation is inhibited when V
DD
is less than
2.5V typical.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) V
DD
power-on delay: When V
DD
has reached its sense level, the device will automatically time-out
5 mS before any write (erase/program) operation.
Data Polling (DQ
7
)- Write Status Detection
The W29S201 includes a data polling feature to indicate the end of a program or erase cycle. When the
W29S201 is in the internal program or erase cycle, any attempt to read DQ
7
of the last word loaded will
receive the complement of the true data. Once the program or erase cycle is completed, DQ
7
will show
the true data. Note that DQ
7
will show logical "0" during the erase cycle, and become logical "1" or true
data when the erase cycle has been completed. Note that is for assynchronous read mode only
(MODE =V
IH
).
Toggle Bit (DQ
6
)- Write Status Detection
In addition to data polling, the W29S201 provides another method for determining the end of a program
cycle. During the internal program or erase cycle, any consecutive attempts to read DQ
6
will produce
alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's
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