
Preliminary W741C20X
Publication Release Date: March 1998
- 23 -
Revision A3
Interrupts
The W741C20X provides five internal interrupt sources (Divider 0, Timer 0, Timer 1, serial I/O) and
two external interrupt sources (
INT
, port RC). Vector addresses for each of the interrupts are located
in the range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are
used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF
and PEF have been set by software, an interrupt is generated. When an interrupt occurs, all of the
interrupts are inhibited until the EN INT or MOV IEF, #I instruction is invoked. The interrupts can also
be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the
hold mode will be released momentarily and interrupt subroutine will be executed. After the RTN
instruction is executed in an interrupt subroutine, the
μ
C will enter hold mode again. The operation
flow chart is shown in Figure 14. The control diagram is shown below.
S
R
Q
S
R
Q
S
R
Q
IEF.0
IEF.1
Interrupt
Process
Circuit
Interrupt
Vector
Generator
004H
008H
020H
IEF.7
Initial Reset
CLR EVF,#I instruction
DIS INT instruction
Initial Reset
MOV IEF,#I
Enable
EN INT
EVF.1
EVF.0
EVF.7
Disable
Divider 0
overflow signal
Timer 0
underflow signal
Timer 1
underflow signal
Figure 13. Interrupt event control diagram
Interrupt Enable Flag (IEF)
The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used
to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these
interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are
unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I
or
EN INT
is executed again. To enable these interrupts, the instructions MOV IEF, #I or EN INT must
be executed again. Otherwise, these interrupts can be disabled by executing DIS INT instruction. The
bit descriptions are as follows:
w
w
w
1
2
3
IEF
4
w
w
5
6
0
w
w
7
Note: W means write only.