
Preliminary W741C20X
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When the interrupt of RC port is accepted, the corresponding event flag (EVF.2) will be reset, but the
content of PSR0 should not be changed except the CLR PSR0 or MOV PEF, #I instruction being
executed or performing the reset function. In addition, the falling edge signal on the pin of port RC
specified by the instruction MOV SEF, #I will cause the device to exit the stop mode. The RD port is
used as the I/O port only.
Refer to Figure 9, Figure 10 and the instruction table for more details.
I/O PIN
RC.n(RD.n)
DATA
BUS
Buffer
Output
PM4.n
(or PM5.n)
MOVA R, RC
(or MOVA R, RD)
instruction
MOV RC, R
(or MOV RD, R)
Instruction
Enable
Enable
Vdd
Input/Output Pin of the RC(RD)
Figure 9. Architecture of RC & RD Input/Output Pins
Port Enable Flag (PEF)
The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be
used to release the hold mode or preform interrupt function, the content of the PEF must be set first.
The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:
PEF
w
w
w
0
1
2
w
3
Note: W means write only.
PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt.
PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt.
PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt.
PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt.
Port Status Register 0 (PSR0)
Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or
cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:
R
R
R
R
0
1
2
3
PSR0
Note: R means read only.