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參數資料
型號: W741C20X
廠商: WINBOND ELECTRONICS CORP
英文描述: 4-BIT MICROCONTROLLER
中文描述: 4位微控制器
文件頁數: 20/84頁
文件大小: 486K
代理商: W741C20X
Preliminary W741C20X
- 20 -
(1)When the SIP R instruction is executed, the data will be loaded from the serial input buffer to
the ACC and RAM first, and bit 1 of port status register 2 will automatically be set to "1" (BUSY
I
= 1). Then the CLKI pin will send out 8 clocks and the data from the DIN pin will be loaded to
SIB at the rising edge of the CLKI pin. After the 8 clocks have been sent, BUSY
I
will be reset to
"0" and EVF.5 will be set to "1." At this time, if IEF.5 has been set (IEF.5 = 1), an interrupt is
executed; if HEF.5 has been set (HEF.5 = 1), the hold state is terminated. Users can check the
status of PSR2.1 (BUSY
I
) to know whether the serial input process is completed or not. If a
serial input process is not completed, and the SIP R instruction is executed again, the data will
be lost. The timing is shown in Figure 11.
T1
T2
T3
T4
CLKI
(RE3)
Data latch
BUSYI
(PSR2.1)
EVF5
Ins.
DIN
(RE2)
SIP R
1
2
3
4
5
6
7
8
Notes : 1. These clocks at the CLKI pin are internal clock and its frequency is Fosc/2.
2. When the internal signal of the data latch equals to "1,"
then the data in SIB will be loaded into RAM and ACC.
Figure 11. Timing of the Serial Input Function (SIP R)
(2)When the SOP R instruction is executed,
the data will be loaded to the serial output buffer
(SOB) and bit 3 of port status register 2 will be set to "1" (BUSY
O
= 1). Then the CLKO pin will
send out 8 clocks and the data in SOB will be sent out at the falling edge of the CLKO pin.
After the 8 clocks have been sent, BUSY
O
will be reset to "0" and EVF.6 will be set to "1." At
this time, if IEF.6 has been set (IEF.6 = 1), an interrupt is executed; if HEF.6 has been set
(HEF.6 = 1), the hold state is terminated. Users can check the status of PSR2.3 (BUSY
O
) to
know whether the serial output process is completed or not. If a serial output process is not
completed, and the SOP R instruction is executed again, the data will be lost. The timing is
shown in Figure 12.
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