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參數資料
| 型號： | W6662CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | CCD(Correlated Double Sampler)/CIS(Contact Image Sensors) Analog Front End Signal Processor.(耦合采樣器／接觸圖象傳感器模擬前端信號處理器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 10 X 10 MM, 2 MM HEIGHT, PLASTIC, QFP-48 |
| 文件頁數： | 9/19頁 |
| 文件大小： | 272K |
| 代理商： | W6662CF |
Preliminary W6662CF
Publication Release Date: December 1998
- 9 -
Revision A1
B. Power down mode
bit [6:0] = don't care.
bit 7 = 1.
The CDSCK1, CDSCK2, ADCCLK and SCLK must hold at stable state after power down mode has
been configured to ensure the W6662 is in low power state. The system must wait at least 10 mS to
ensure that the device is power up completedly if the configuration register is programmed with bit 7
= 0.
PGA Registers
The mapping of PGA registers and PGA_code is:
bit [5:0] PGA_code, bit 5 is MSB, bit 0 is LSB.
bit [7:6] reserved (must set to 0).
The offset registers are described in PGA gain/offset adjustment section.
Fig. 6-4 Configuration Serial Interface Modes.
(a). Three-wired Interface Mode Selected.
(b). Four-wired Interface Mode Selected.
W6662
SCLK
SEN
SDIO
SMS
Micro-controller
or
System Controller
or
Core Chip
May drive another peripherals
chip select
W6662
SCLK
SEN
SDI
SDO
May drive another peripherals
chip select
Micro-controller
or
System Controller
or
Core Chip
DRVDD
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