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參數資料
| 型號： | W6662CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | CCD(Correlated Double Sampler)/CIS(Contact Image Sensors) Analog Front End Signal Processor.(耦合采樣器／接觸圖象傳感器模擬前端信號處理器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 10 X 10 MM, 2 MM HEIGHT, PLASTIC, QFP-48 |
| 文件頁數： | 12/19頁 |
| 文件大小： | 272K |
| 代理商： | W6662CF |
Preliminary W6662CF
- 12 -
7.5 Analog Characteristics (measures from analog input to ADC output), continued
PARAMETER
SYM.
MIN.
TYP
57
MAX.
UNITS
TEST CONDITIONS
Signal to Noise Ratio
from analog I/P to ADC O/P
SNR
dB
Note 3
: Typical figure are at V
DD
= 5V and temperature = 25
°
C and are for design aid only, not guaranteed and not subject to
production testing.
Notes:
1: 3V input span configured, PGA gain = 1, offset = 0 and measures from analog input to ADC output.
2: All steps of PGA gain and offset are monotonic.
3. 3V input span configured and analog 3V signal range.
7.5.1 Analog Characteristics (measures from ADC input to ADC output)
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNITS
TEST CONDITIONS
Analog to Digital Converter
Maximum Conversion Rate
SPS
3
MHz
Resolution
12
Bits
Integral Nonlinearity
INL
+/- 1.5
LSB
Note
Differential Nonlinearity
DNL
+/- 1
LSB
Note
Note: This is measured on the engineer sample and do not subject to production testing.
7.6 Timing Characteristics
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNITS
NOTES
Clock Input Requirement
Conversion Rate
t
CVR
332
nS
ADCCLK High pulse width
t
ADCH
166
nS
ADCCLK Low pulse width
t
ADCL
166
nS
Clamp pulse width
t
CLP
40
nS
Sample data pulse width
t
SPD
40
nS
Clamp to Sample
t
C2S
20
nS
Sample data to ADC Convert
t
S2AD
80
nS
ADC Convert to Clamp
t
S2C
t
S2AD
+20
nS
Analog signal Capture Delay of
CDS clocks
t
ACD
10
nS
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