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參數資料
| 型號： | W6662CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | CCD(Correlated Double Sampler)/CIS(Contact Image Sensors) Analog Front End Signal Processor.(耦合采樣器／接觸圖象傳感器模擬前端信號處理器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 10 X 10 MM, 2 MM HEIGHT, PLASTIC, QFP-48 |
| 文件頁數： | 4/19頁 |
| 文件大小： | 272K |
| 代理商： | W6662CF |
Preliminary W6662CF
- 4 -
6. FUNCTIONAL DESCRIPTIONS
Figure 4 is the block diagram of W6662, it consists of three channel clamp circuit for CDS mode, a
multiplexer to mux 3-channel inputs and outputs to a correlated double sampling (CDS), a
programmable gain control and offset adjustment amplifier, a 12-bit analog-to-digital converter.
Bandgap reference circuit generate voltage reference signals for input signals clampping and
correlated sampling use (in CDS mode), for offset D/A converter and output A/D converter use. The
select signals SEL1 and SEL0 are used to select the offset registers and gain registers, the input
channels may be selected simultaneously.
6.1 Clamp Circuit
The capacitor between the output of CCD/CIS device and W6662 is used to block the DC voltage
(even as high voltage). The clamp circuit is used to remove unwanted common-mode voltage in the
input pixel data and to get a maximum input signal span when the input is driven by CCD device as
shown in Figure 6-1. The input pins of W6662 are clampped to a internal offset voltage while valid
pixel signal is input. The clamp switches at three channels of figure 6-1 are turn on whenever
CDSCK1 goes high. Figure 6-2 shows the waveform between output of CCD device and input of
W6662, the voltage change on the capacitor will be clampped.
The value of input capacitor is calculated as follows:
t
CLP
C
MAX
=
(RON + R
CCDS
)
×
ln (V
C
/V
CLPTolerance
)
I
BIAS
×
t
C2I
C
MIN
=
dV
where
C
MAX
is the maximum capacitor value.
C
MIN
is the minimum capacitor value.
t
CLP
is the high pulse width of the CDSCK1 clock input.
R
ON
is switch resistance during clampping and is equivalent to 5K.
R
CCDS
is the source resistance of CCD device.
V
C
is the voltage change on the input capacitor must be clampped.
V
CLPTolerance
is the tolerance voltage error at the end of clampping.
I
BIAS
is the input leakage current on the input of the W6662 device.
dV is the maximum voltage drift on the input of the W6662 device.
t
C2I
is the time stamp from the end of clampping point to the acture input data sampling point, equal
to t
C2S
+ t
SPD
+ t
ACD
or may be approximated as conversion time t
CVR
.
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